MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 145

• Manufacturer Part Number: MC912DT128ACPV
• Description: IC 8MHZ 16 BIT MICROCONTROLLER
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DT128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: KMC912DT128ACPV; Q1195202

10.8.4 Clock Monitor Reset
10.9 Effects of Reset
10.9.1 Operating Mode and Memory Map
10.9.2 Clock and Watchdog Control Logic
MC68HC912DT128A — Rev 4.0
MOTOROLA
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The SMODN,
MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
The COP watchdog system is enabled, with the CR[2:0] bits set for the
longest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used. The DLY control bit is set to specify an oscillator start-up delay
upon recovery from STOP mode.
Freescale Semiconductor, Inc.
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Resets and Interrupts
Resets and Interrupts
Effects of Reset
Technical Data
145