MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 371
MC912DT128ACPV
Manufacturer Part Number
MC912DT128ACPV
Description
IC 8MHZ 16 BIT MICROCONTROLLER
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DT128ACPV
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
KMC912DT128ACPV
Q1195202
Q1195202
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19.4.3 Sample and Hold Stage
19.4.4 Analog-to-Digital Converter Submodule
19.4.5 Clock Prescaler Function
MC68HC912DT128A — Rev 4.0
MOTOROLA
A Sample and Hold (S/H) stage accepts the analog signal from the input
multiplexer and stores it as a capacitor charge on a storage node in the
module. The sample process uses a three stage approach:
This charge redistribution method eliminates the need for external
sample-and-hold circuitry.
The Analog-to-Digital (A/D) Machine uses a successive approximation
A/D architecture to perform analog to digital conversions. The resolution
of the A/D converter is selectable at either 8 or 10 bits. It functions by
comparing the stored analog sample potential with a series of digitally
generated analog potentials (using CDAC & RDAC arrays). By following
a binary search algorithm, the converter quickly locates the
approximating potential that is nearest to the sampled potential. At the
end of the conversion process (10 module clocks for 8-bit, 12 module
clocks for 10-bit), the Successive Approximation Register (SAR)
contains the nearest approximation to the sampled signal, given the
resolution of the A/D converter, and is transferred to the appropriate
results register in the selected format.
To keep the ATD module clock within the specified frequency range
(note: there is a minimum and maximum frequency), a clock prescaler
function is available. This function divides the system PCLK by a
1. The input signal is sampled onto a sample capacitor (for 2 module
2. The sample amplifier quickly charges the storage node with a
3. The input signal is connected directly to the storage node to
Freescale Semiconductor, Inc.
For More Information On This Product,
clocks).
copy of the sample capacitor potential (for 4 module clocks).
complete the sample for high accuracy (for 2, 4, 8 or 16 module
clocks). Longer sample times allow accurate measurement of
higher impedance sources.
Analog-to-Digital Converter
Go to: www.freescale.com
Analog-to-Digital Converter
Functional Description
Technical Data
371
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