MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 395

• Manufacturer Part Number: MC912DT128ACPV
• Description: IC 8MHZ 16 BIT MICROCONTROLLER
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DT128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: KMC912DT128ACPV; Q1195202

Technical Data — MC68HC912DT128A
20.1 Contents
20.2 Introduction
20.3 Instruction Queue
MC68HC912DT128A — Rev 4.0
MOTOROLA
20.2
20.3
20.4
20.5
20.6
Development support involves complex interactions between
MC68HC912DT128A resources and external development systems.
The following section concerns instruction queue and queue tracking
signals, background debug mode, and instruction tagging.
The CPU12 instruction queue provides at least three bytes of program
information to the CPU when instruction execution begins. The CPU12
always completely finishes executing an instruction before beginning to
execute the next instruction. Status signals IPIPE[1:0] provide
information about data movement in the queue and indicate when the
CPU begins to execute instructions. This makes it possible to monitor
CPU activity on a cycle-by-cycle basis for debugging. Information
available on the IPIPE[1:0] pins is time multiplexed. External circuitry
can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges.
20-1
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the meaning of data on the pins.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
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Development Support
Section 20. Development Support
Technical Data
Table
395