MC68HC908AP64CB Freescale Semiconductor, MC68HC908AP64CB Datasheet - Page 255

• Manufacturer Part Number: MC68HC908AP64CB
• Description: IC MCU 64K FLASH 8MHZ 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AP64CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: DEMO908AP64E - BOARD DEMO FOR 908AP64DEMO908AP64 - BOARD DEMO FOR 908AP64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.7 I/O Registers
These I/O registers control and monitor ADC operation:
15.7.1 ADC Status and Control Register
Function of the ADC status and control register is described here.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
ADCO — ADC Continuous Conversion Bit
ADCH[4:0] — ADC Channel Select Bits
Freescale Semiconductor
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When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADSCR is written, or whenever the ADC clock control
register is written, or whenever the ADC data register low, ADRLx, is read.
If the AIEN bit is logic 1, the COCO bit always read as logic 0. ADC interrupt will be generated at the
end if an ADC conversion. Reset clears the COCO bit.
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register, ADR0, is read or the ADSCR is written. Reset clears the AIEN bit.
When set, the ADC will convert samples continuously and update the ADC data register at the end of
each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
This bit should not be set when auto-scan mode is enabled; i.e. when ASCAN=1.
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels when not in auto-scan
mode. The five channel select bits are detailed in
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
1 = Continuous ADC conversion
0 = One ADC conversion
ADC status and control register (ADSCR) — $0057
ADC clock control register (ADICLK) — $0058
ADC data register high:low 0 (ADRH0:ADRL0) — $0059:$005A
ADC data register low 1–3 (ADRL1–ADRL3) — $005B–$005D
ADC auto-scan control register (ADASCR) — $005E
Address:
Care should be taken when using a port pin as both an analog and a digital
input simultaneously to prevent switching noise from corrupting the analog
signal. Recovery from the disabled state requires one conversion cycle to
stabilize.
Reset:
Read:
Write:
Figure 15-3. ADC Status and Control Register (ADSCR)
COCO
$0057
0
AIEN
0
MC68HC908AP Family Data Sheet, Rev. 4
ADCO
0
NOTE
ADCH4
1
Table
ADCH3
15-1.
1
ADCH2
1
ADCH1
1
ADCH0
1
I/O Registers
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