MC68HC908AP64CB Freescale Semiconductor, MC68HC908AP64CB Datasheet - Page 84

• Manufacturer Part Number: MC68HC908AP64CB
• Description: IC MCU 64K FLASH 8MHZ 42SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AP64CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: DEMO908AP64E - BOARD DEMO FOR 908AP64DEMO908AP64 - BOARD DEMO FOR 908AP64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGM)
84
1. Choose the desired bus frequency, f
2. Choose a practical PLL reference frequency, f
3. Calculate N:
4. Calculate and verify the adequacy of the VCO and bus frequencies f
solve for the other.
The relationship between f
where P is the power of two multiplier, and can be 0, 1, 2, or 3
the reference is 32.768kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f
and R = 1. If f
practical choices of f
RCLK
R
cannot meet this requirement, use the following equation to solve for R with
RCLK
=
round R
, and choose the f
f
BUS
VCLK
MC68HC908AP Family Data Sheet, Rev. 4
and f
N
MAX
=
=
2
P
×
VCLK
round
BUSDES
f
f
×
⎧
⎨
⎩
VCLK
VCLK
f
⎛
⎜
⎝
BUS
f
f
------------------------- -
CGMPCLK
VCLKDES
is governed by the equation:
f
⎛
⎜
⎝
RCLK
R f
------------------------------------ -
=
=
=
RCLK
, or the desired VCO frequency, f
f
×
RCLK
2
----------- f
2
----------- f
---------- -
2
f
RCLK
VCLK
P
P
R
R
P
VCLKDES
VCLK
N
N
×
that gives the lowest R.
⎞
⎟
⎠
=
(
(
×
4
–
, and the reference clock divider, R. Typically,
2
RCLK
RCLK
integer
2
, and the reference frequency, f
P
P
RCLK
×
⎞
⎟
⎠
4
)
)
×
/R. For stability and lock time reduction,
RCLK
⎛
⎜
⎝
f
f
------------------------- -
BUS
VCLKDES
f
RCLK
to an integer divisor of f
Chapter 22 Electrical
VCLK
RCLK
⎞
⎟
⎠
⎫
⎬
⎭
and f
to a value determined
Freescale Semiconductor
VCLKDES
BUS
.
RCLK
; and then
BUSDES
, is
,