HD6412332VFCBL25 Renesas Electronics America, HD6412332VFCBL25 Datasheet - Page 222
HD6412332VFCBL25
Manufacturer Part Number
HD6412332VFCBL25
Description
IC H8S MCU ROMLESS 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD6412332VFCBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 2 Instruction Descriptions
2.2.58 (3)
SHAR (SHift Arithmetic Right)
Operation
Rd (right arithmetic shift)
Assembly-Language Format
SHAR.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. Bit
0 shifts into the carry flag. Bit 15 shifts into itself. Since bit 15 remains unaltered, the sign does
not change.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 206 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAR (W)
Mnemonic
SHAR.W
MSB
b15
Rd
Operands
Rd
. . . . . .
1st byte
1
1
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 0.
2nd byte
9
Instruction Format
cleared to 0.
cleared to 0.
—
I
rd
UI H
—
LSB
b0
—
3rd byte
—
U
C
N
4th byte
Shift Arithmetic
Z
V
0
States
No. of
C
1
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