M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 352

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
1
6
Version
C
8 /
0
G
o r
Page 109 Figure 1.14.6 Note 1 It is indeterminate when reset --> addition
Page 112 Figure 1.15.2 Dead time timer-->Note 1 addition, Timer B2 interrupt occurrence
Page 113 Notes 2, 3 --> addition
Page 114 three-phase waveform mode --> three phase PWM output mode
Page 128 Figure 1.16.5 UARTi bit rate generator --> Note 2 addition
Page 128 Figure 1.16.5 UARTi transmit buffer register, UARTi bit rate generator-->Note 1
Page 129 Figure 1.16.6 UARTi transmit/receive mode register-->Note 2 addition in CKDIR of
Page 133 Figure 1.16.10 UART transmit/receive control register 2-->Note delete
Page 136 Note 2, Page 143 Note 3 ... the UARTi receive interrupt request bit is not set to "1"
Page 145 Figure 1.18.1 UARTi transmit/receive mode register (i=0,1) --> Note 1 addition,
Page 157 On the 12th line, ... allocated to bit 3 in UART2 transmission buffer register 1
Page 161 < Master Mode (TxDi and RxDi are selected, DINC = 0) >
Page 165 Table 1.21.1 Absolute precision --> change
Page 170 Table 1.21.3 Reading of result of A/D converter --> (at any time) addition
Page 173 Table 1.21.6 Input pin --> change to AN
Page 182 On the second line from the bottom, ..., and dummy cycle for refresh ... --> ..., and
Page 183 Figure 1.25.2 is partly revised.
Page 189 On the 18th and 27th lines, page 194 Port Pi direction register Note 2, page 196
Page 203 Figure 1.26.13 is partly revised.
Page 207, 208 Timer A (event counter mode) --> (3) addition, Timer A (one-shot timer mode)
Page 209 Timer B (pulse period/pulse width measurement mode) --> (3) addition
Page 212 to 214 (2) NMI interrupt •The NMI pin also serves as P8
Page 215 Explanation of (3) is partly revised.
Page 215 HOLD signal --> addition
Page 216 DRAM controller --> addition
u
p
ing) --> "Note 2 Timer A2 is fixed to ... multiply-by-4 processing operation." is added,
note 3 change
frequency set counter-->Note 3 addition
addition
UART mode
--> ... the UARTi receive interrupt request bit will not change
UARTi transmit/receive mode register (i=2 to 4) --> Note 2 addition
(address 033F
(address 033E
addition
processing necessary for dummy cycle to refresh DRAM ...
Port Pi register Note 1 ... for setting of bus control such as address bus and data bus is
... --> of pins A
WRH/BHE/CASH, RD/DW, BCLK/ALE/CLK
RDY are ...
--> (2) changes to (3), (2) and (4) addition
_______
_______
..., and the STxDi, SRxDi and CLKi pins ...--> ..., and the TxDi, RxDi and CLKi
pins ...
(3) Address match interrupt
(4) External interrupt, (5) Rewrite the interrupt control register --> addition
__________
_______
"; Interrupt completed" on page 77 --> addition
_______
________
--> addition
16
0
16
to A
) ...
) ... --> ... allocated to bit 11 in UART2 transmission buffer register
_____ _____
22
, A
_____
23
, D
Contents for change
0
to D
________
From "• To return from an interrupt..." to
15
C - 10
, MA
0
OUT
to MA
0
to AN
, HLDA/ALE, HOLD, ALE/RAS, and
_________
12
7
, CS0 to CS 3, WRL/WR/CASL,
, With emphasis on the pin -->
_______
5
, ... •Signal of "L" level ...
_______
_________
_______
_____ _________
_______
Revision History
Revision
date