M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 71

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
1 .
0
9.3 Hardware Interrupts
C
9
(2) Peripheral I/O interrupts
0 .
There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts.
• Reset
• NMI interrupt
• Watchdog timer interrupt
• Address-match interrupt
• Single-step interrupt
• Bus collision detection, start/stop condition detection interrupts (UART2, UART3, UART4), fault
• DMA0 through DMA3 interrupts
• Key-input interrupt
• A/D conversion interrupt
• UART0, UART1, UART2/NACK, UART3/NACK and UART4/NACK transmission interrupt
• UART0, UART1, UART2/ACK, UART3/ACK and UART4/ACK reception interrupt
• Timer A0 interrupt through timer A4 interrupt
• Timer B0 interrupt through timer B5 interrupt
• INT0 interrupt through INT5 interrupt
8 /
B
0
(1) Special interrupts
error interrupts (UART3, 4)
0
_______
0
A reset occurs when the RESET pin is pulled low.
______
This interrupt occurs when the NMI pin is pulled low.
This interrupt is caused by the watchdog timer.
This interrupt occurs immediately before the instruction at the address indicated by the address match
interrupt register is executed while the address match interrupt enable bit is set to “1”.
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
This interrupt is used exclusively for debugger purposes, do not use it in other circumstances. A single-
step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated after one
instruction is executed.
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
43 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
This is an interrupt that the serial I/O bus collision detection generates. When I
start, stop condition interrupt is selected. When SS pin is selected, fault error interrupt is selected.
These are interrupts that DMA generates.
A key-input interrupt occurs if an “L” is input to the KI pin.
This is an interrupt that the A/D converter generates.
These are interrupts that the serial I/O transmission generates.
These are interrupts that the serial I/O reception generates.
These are interrupts that timer A generates
These are interrupts that timer B generates.
An INT interrupt selects a edge sense or a level sense. In edge sense, an INT interrupt occurs if either
a rising edge or a falling edge or a both edge is input to the INT pin. In level sense, an INT interrupt
occurs if either an "H" level or an "L" level is input to the INT pin.
1
Special interrupts are nonmaskable interrupts.
A
8
G
u
7
o r
_____
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
5
Page 58
________
____________
f o
3
2
9
______
_____
___
_____
_____
_____
2
9. Interrupt Outline
C mode is selected,
_____