M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 355

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
1
6
Rev.1.0
Version
C
8 /
0
G
o r
Page 136 Figure 16.12 Special mode register 3 'SDAi digital delay time set bit' --> revised
Page 150 Figure18.5 /P --> P revised
Page 152 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Page 153 (a) Function for outputting a parity error signal
Page 160 the baud rate generator --> the UARTi bit rate generator
Page 160 UART2 Special Mode Register 2 (Address 0336
Page 161 UART2 Special Mode Register 3(Address 0335
Page 163 Figure 20.6 Special mode register 3 'SDAi digital delay time set bit' --> revised
Page 176 Set the function select register A... --> Set the function select register A3...
Page 193 Figure 26.2, P74, P75, P80 move to (inside dotted-line included)
Page 208 Timer --> added
Page 209 (5) If an exernal triger input is used to start counting, the next external triger input
Page 210 Timer B (pulse period/pulse width measurement mode)
u
p
001: 1 to 2 cycles of 1/f(XIN)
010: 1 to 2 cycles of 1/f(XIN)
011: 1 to 2 cycles of 1/f(XIN)
100: 1 to 2 cycles of 1/f(XIN)
101: 1 to 2 cycles of 1/f(XIN)
110: 1 to 2 cycles of 1/f(XIN)
111: 1 to 2 cycles of 1/f(XIN)
Diagram revised
With the error signal output enable bit ... TxDi pin when a parity error is detected.
--> During reception,with the error signal output enable bit ... TxDi pin when a parity
error is detected.
In step with this function, ... of a parity error signal. --> deleted
Therefore parity error signals ... interrupt program. --> added
And during transmission, ... of the transfer clock. --> added
001: 1 to 2 cycles of 1/f(XIN)
010: 1 to 2 cycles of 1/f(XIN)
011: 1 to 2 cycles of 1/f(XIN)
100: 1 to 2 cycles of 1/f(XIN)
101: 1 to 2 cycles of 1/f(XIN)
110: 1 to 2 cycles of 1/f(XIN)
111: 1 to 2 cycles of 1/f(XIN)
(4) --> added
SDAi, UART2 --> UARTi revised
baud rate generator stops counting. -->the count stops
Register 2(i=2 to 4) (Address 0336
must be avoided within 300ns before the timer A reaches "0000h". --> added
Register 3(i=2 to 4 )(Address 0335
SDA2 --> SDSi revised
Contents for change
C- 13
16
,0326
16
16
,02F6
,0325
16
16
) --> UARTi Special Mode
16
) --> UARTi Special Mode
16
), SCL2 --> SCLi, SDA2 -->
,02F5
16
)
Revision History
Revision
02/08/'05
date