M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 47

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Figure 7.2 Example of address bus and chip select signal outputs (Separate bus)
6
1 .
0
C
9
0 .
8 /
B
The chip select signal turns “L” (active) in synchronize with the address bus. However, its turning “H”
depends on the area accessed in the next cycle. Figure 7.2 shows the output examples of the address
bus and chip select signals.
0
(Example 3) After accessing the external area, only the address bus is
0
(Example 1) After accessing the external area, the address bus and chip
0
1
A
The following example shows the other chip select signal accessing
area (j) in the cycle after having accessed external area (i). In this
case, the address bus and chip select signal both change between the
two cycles.
8
G
Address bus
u
7
Address bus
Chip select
o r
. g
0 -
Chip select
Chip select
Data bus
u
Data bus
1
0
p
0
, 2
(CSi)
changed in the next cycle. (The chip select signal does not
change.)
The following example shows the same chip select signal
accessing area (i) in the cycle after having accessed
external area (i). In this case, the address bus changes
between the two cycles, but the chip select signal does not.
0
(CSi)
(CSj)
select signal both are changed in the next cycle.
2
0
Note: These examples show the address bus and chip select signal for two consecutive cycles.
0
5
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By combining these examples, chip select signal can be extended beyond two cycles.
Access to
external
area (i)
Address
Address
Access to
external
area (i)
Data
Data
Access to
external
area (i)
f o
Access to
external
area (j)
3
Data
2
Data
9
(Example 2) After accessing the external area, only the chip select signal
(Example 4) After accessing the external area, the address bus and chip
Address bus
Address bus
Chip select
Chip select
Data bus
is changed in the next cycle. (The address bus does not
change.)
The following example shows the CPU accesses the internal
ROM/RAM area in the cycle after having accessed external
area. In this case, the chip select signal changes between the
two cycles but the address bus does not.
Data bus
select signal both are not changed in the next cycle.
The following example shows CPU does not access any
area in the cycle after having accessed external area (no
instruction pre-fetch is occurred). In this case, the address
bus and the chip select signal do not change between the
two cycles.
Access to
external
area
Address
Address
Data
Data
No access
7. Bus