HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 199

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.5.2
Table 7.7 summarizes the registers of port 8.
Table 7.7
Address*
H'EE007
H'FFFD7
Note:
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
When bits in P8DDR bit are set to 1, P8
P8DDR are cleared to 0, the corresponding pins become input ports.
Bit
Initial value
Read/Write
Port 8
* Lower 20 bits of the address in advanced mode.
Register Descriptions
Port 8 Registers
Name
Port 8 data direction register
Port 8 data register
⎯
⎯
7
1
Port 8 pins
P8 /
P8 /
P8 /
P8 /
P8 /
4
3
2
1
0
Reserved bits
IRQ
CS
CS
CS
CS
0
1
2
3
0
Figure 7.4 Port 8 Pin Configuration
/
/
/
IRQ / ADTRG
IRQ
IRQ
⎯
⎯
6
1
3
2
1
4
⎯
⎯
to P8
5
1
1
P8 (input)/
P8 (input)/
P8 (input)/
P8 (input)/
P8 (input/output)/
P8 DDR
become CS
4
3
2
1
0
4
W
Abbreviation
P8DDR
P8DR
4
1
CS
CS
CS
CS
Rev.4.00 Aug. 20, 2007 Page 153 of 638
P8 DDR
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
0
0
1
2
3
3
to CS
W
3
0
(output)
(output)/
(output)/
(output)/
IRQ
3
0
output pins. When bits in
P8 DDR
(input)
IRQ
IRQ
IRQ
R/W
W
R/W
2
W
2
0
3
2
1
(input) / ADTRG (input)
(input)
(input)
P8 DDR
Initial Value
H'F0
H'E0
REJ09B0395-0400
1
W
1
0
7. I/O Ports
P8 DDR
0
W
0
0