HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 13
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Item
4.8 Usage Note
Figure 4.3 Operation When
SP Value Is Odd
5.6.5 IRQ Interrupt
5.6.6 NMI Interrupts Usage
Notes
6.3.4 Operation in
Transitions to Power-Down
Modes
7.6.4 Wait Control
(2) Pin Wait Insertion
9.2.5 DTC Transfer Count
Register A (CRA)
10.1.2 Port 1 Data Register
(P1DR)
Page
126
156
156
161
191
285
310
Revision (See Manual for Details)
Figure amended
5.6.5 added
5.6.6 added
Description amended
•
Description amended
Setting the WAITE bit in BCRL to 1 enables wait insertion by
means of the WAIT pin.
Description amended
In repeat mode or block transfer mode, the CRA is divided
into two parts; the upper 8 bits (CRAH) and the lower 8 bits
(CRAL). In repeat mode, CRAH holds the number of
transfers while CRAL functions as an 8-bit transfer counter
(1 to 256). In block transfer mode, CRAH holds the block
size while CRAL function as an 8-bit block size counter (1 to
256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the
count reaches H'00. This operation is repeated.
Table amended
SP
Bit
7
6
5
4
3
2
1
0
SP set to H'FFFEFF
When the SLEEP instruction causes a transition from
high speed
Bit Name
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
TRAPA instruction executed
Initial Value
0
0
0
0
0
0
0
0
mode to subactive mode (figure 6.2 (B)).
SP
Data saved above SP
Rev. 6.00 Mar. 18, 2010 Page xi of lx
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CCR
PC
Description
Output data for a pin is stored when the pin is
specified as a general purpose output port.
MOV.B R1L, @-ER7 executed
SP
REJ09B0054-0600
Contents of CCR lost
R1L
PC
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
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