HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 831
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
5
4
3
2
NESEL
SUBSTP
RFCUT
—
Bit Name
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Noise Elimination Sampling Frequency Select
This bit selects the sampling frequency of the
subclock (φ
is sampled by the clock (φ) generated by the system
clock oscillator
Set 0 when φ is 5 MHz or higher. Set 1 when φ is 2.1
MHz or lower. Any value can be set when φ is 2.1 to
5 MHz.
0: Sampling using 1/32 × φ
1: Sampling using 1/4 × φ
Subclock Enable
This bit enables/disables subclock generation. This
bit should be set to 1 when subclock is not used.
0: Enables subclock generation.
1: Disables subclock generation.
Oscillation Circuit Feedback Resistance Control Bit
Selects whether or not built-in feedback resistance
and duty adjustment circuit of the system clock
generator are used when an external clock is input.
Do not access when the crystal resonator is used.
After setting this bit in the external clock input state,
enter software standby mode, watch mode, or
subactive mode. When software standby mode,
watch mode, or subactive mode is entered, switch
whether or not built-in feedback resistance and duty
adjustment circuit are used.
0: Built-in feedback resistance and duty adjustment
1: Built-in feedback resistance and duty adjustment
Reserved
This bit is readable/writable, but the write value
should always be 0.
circuit of the system clock generator used.
circuit of the system clock generator not used.
Rev. 6.00 Mar. 18, 2010 Page 769 of 982
SUB
) generated by the subclock oscillator
Section 23 Clock Pulse Generator
REJ09B0054-0600
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