HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 616
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 616 of 1048
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Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 554 of 982
REJ09B0054-0600
Bit
4
3
2
Bit Name
O/E
STOP
MP
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of
the next transmit character.
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
For details, see section 15.5, Multiprocessor
Communication Function.
When even parity is set, parity bit addition is
performed in transmission so that the total
number of 1 bits in the transmit character plus
the parity bit is even. In reception, a check is
performed to see if the total number of 1 bits in
the receive character plus parity bit is even.
When odd parity is set, parity bit addition is
performed in transmission so that the total
number of 1 bits in the transmit character plus
the parity bit is odd. In reception, a check is
performed to see if the total number of 1 bits in
the receive character plus the parity bit is odd.
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