HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 847
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4. Supported only by the H8S/2258 Group.
5. The analog output value does not satisfy the specified D/A absolute accuracy when D/A
Program execution state
is halted (retained). However, the H8S/2258 Group, H8S/2238B, and H8S/2236B
satisfy the specified D/A absolute accuracy.
Notes:
Reset state
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 0
After the oscillation
settling time
(STS2 to 0), clock
switching exception
processing
MRES pin = High
When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs when RES is
driven Low. At any state except hardware standby mode and power-on reset state, a transition to
the manual reset state occurs when the MRES pin is driven Low.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
Always select high-speed mode before making a transition to watch mode or sub-active mode.
1.
2.
3.
reset state
NMI, IRQ7 to IRQ0, and WDT1 interrupts.
NMI, IRQ7 to IRQ0, and WDT1, WDT0, and TMR3 to TMR0 interrupts.
NMI, IRQ7 to IRQ0
Manual
SCK2 to
SCK0 = 0
High-speed mode
Sub-active mode
Medium-speed
(main clock)
(main clock)
(subclock)
Figure 24.1 Mode Transition Diagram
mode
: Transition after exception processing
SCK2 to
SCK0 ≠ 0
SLEEP instruction
SSBY = 1, PSS = 1
DTON = 1, LSON = 1
Clock switching
exception processing
reset state
Power on
RES pin = High
SLEEP instruction
External
interrupt *
Interrupt *
LSON bit = 0
SLEEP instruction
SLEEP
instruction
STBY pin = High
RES pin = Low
Interrupt *
Interrupt *
LSON bit = 1
SLEEP
instruction
All interrupt
SLEEP
instruction
3
1
Rev. 6.00 Mar. 18, 2010 Page 785 of 982
2
1
Section 24 Power-Down Modes
: Low power dissipation mode
SSBY = 0, LSON = 0
Program-halted state
SSBY = 1,
PSS = 0, LSON = 0
SSBY = 0,
PSS = 1, LSON = 1
SSBY = 1,
PSS = 1, DTON = 0
STBY pin = Low
Sub-sleep mode
standby mode
standby mode
Watch mode
Sleep mode
(main clock)
(subclock)
(subclock)
Hardware
Software
REJ09B0054-0600
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