R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 197
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.29
14.3.2
Table 14.22
i = 0 or 1
Input Capture Function
Output Compare Function Compare match with TRDi register
PWM Mode
Reset Synchronous PWM
Mode
Complementary PWM
Mode
PWM3 Mode
Function and Mode
The TRDGRCi register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register
can be used as the buffer register of the TRDGRBi register by the BFCi and BFDi bits in the TRDMR register.
Buffer operation depends on modes. Table 14.22 lists the Buffer Operation in Each Mode.
Figure 14.29 shows the Buffer Operation in Input Capture Function, and Figure 14.30 shows the Buffer
Operation in Output Compare Function.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
i = 0 or 1
The above applies to the following conditions:
• The BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of
• The IOA2 to IOA0 bits in the TRDIORAi register are set to 100b (input capture at the falling edge).
Buffer Operation
the TRDGRAi register.)
Buffer Operation in Each Mode
Buffer Operation in Input Capture Function
TRDGRAi register
TRDGRCi register
TRDIOAi input
TRDi register
TRDIOAi input
(input capture signal)
Page 175 of 501
(buffer)
Input capture signal input
and TRDGRAi (TRDGRBi) register
Compare match withTRD0 register
and TRDGRA0 register
• Compare match with TRD0 register
• TRD1 register underflow
Compare match with TRD0 register
and TRDGRA0 register
and TRDGRA0 register
TRDGRCi
register
(buffer)
Transfer Timing
n-1
m
TRDGRAi
register
n
Transfer
Transfer
Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRB0, TRDGRA1 and
TRDGRB1 registers
Transfer content in buffer register to
TRDGRA0, TRDGRB0, TRDGRA1
and TRDGRB1 registers
m
n
Transfer Register
n+1
TRDi
14. Timers
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