R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 250
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.80
Timer RD Control Register 0
b7 b6 b5 b4
NOTES:
0 0 1
1.
2.
3.
This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
This bit is enabled w hen the TCK2 to TCK0 bits are set to “101b” (TRDCLK input) and the STCLK bit in the TRDFCR
register is set to 1 (external clock input enabled).
The TRDCR1 register is not used in reset synchronous PWM mode.
b3 b2
TRDCR0 Register in Reset Synchronous PWM Mode
b1 b0
Bit Symbol
TRDCR0
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
TCK0
TCK1
TCK2
Page 228 of 501
(3)
Count source selection bit
External clock edge selection
bit
TRD0 counter clear selection bit
(2)
Address
Bit Name
0140h
b2 b1b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set
Set to 001b (TRD0 register clear at the
compare match w ith TRDGRA0 register) in
reset synchronous PWM mode.
After Reset
Function
(1)
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
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