R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 350
![IC R8C/22 MCU FLASH 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.27
IIC Bus Interrupt Enable Register
b7 b6 b5 b4
NOTES:
1.
2.
An overrun error interrupt request is generated w hen the clock synchronous format is used.
Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
b3 b2 b1
ICIER Register
b0
Bit Symbol
ACKBR
Symbol
ACKBT
NAKIE
ACKE
Page 328 of 501
ICIER
STIE
TEIE
RIE
TIE
Transmit acknow ledge
select bit
Receive acknow ledge bit
Acknow ledge bit judgment
select bit
Stop condition detection
interrupt enable bit
NACK receive interrupt
enable bit
Receive interrupt enable
bit
Transmit end interrupt
enable bit
Transmit interrupt enable
bit
Address
Bit Name
00BBh
0 : 0 is transmitted as acknow ledge bit in receive
1 : 1 is transmitted as acknow ledge bit in receive
0 : Acknow ledge bit w hich is received from
1 : Acknow ledge bit w hich is received from
0 : Value of receive acknow ledge bit is ignored
1 : When receive acknow ledge bit is set to 1,
0 : Disables stop condition detection interrupt
1 : Enables stop condition detection interrupt
0 : Disables NACK receive interrupt request and
1 : Enables NACK receive interrupt request and
0 : Disables receive data full and overrun
1 : Enables receive data full and overrun
0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
0 : Disables transmit data empty interrupt request
1 : Enables transmit data empty interrupt request
mode
receive device in transmit mode is set to 0
receive device in transmit mode is set to 1
and continuous transfer is performed
continuous transfer is halted
request
request
arbitration lost / overrun error interrupt request
arbitration lost / overrun error interrupt request
error interrupt request
error interrupt request
mode
(2)
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(1)
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RO
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