MPC5553MZP132 Freescale Semiconductor, MPC5553MZP132 Datasheet - Page 38

• Manufacturer Part Number: MPC5553MZP132
• Description: IC MCU MPC5553 REV A 416-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC55xx Qorivvar

Specifications of MPC5553MZP132

• Core Processor: e200z6
• Core Size: 32-Bit
• Speed: 132MHz
• Connectivity: CAN, EBI/EMI, Ethernet, SCI, SPI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 220
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.65 V
• Data Converters: A/D 40x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-PBGA
• Processor Series: MPC5xxx
• Core: e200z6
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 7-Wire, DSPI, ESCI
• Maximum Clock Frequency: 132 MHz
• Number Of Timers: 56
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5553EVBISYS - KIT EVAL ISYSTEMS MPC5553MPC5553EVBGHS - KIT EVAL GREEN HILLS SOFTWAREMPC5553EVB - KIT EVAL MPC5553MZP132MPC5553EVBE - BOARD EVAL FOR MPC5553
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical Characteristics
3.13.7
1
2
3.13.8
38
Spec
Spec
eMIOS timing specified at: V
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
1
2
3
4
5
6
7
8
1
2
SCK cycle time
PCS to SCK delay
After SCK delay
SCK duty cycle
Slave access time
(SS active to SOUT driven)
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
PCSx to PCSS time
PCSS to PCSx time
eMIOS input pulse width
eMIOS output pulse width
eMIOS Timing
DSPI Timing
eMIOS
output
eMIOS input
Characteristic
3, 4
6
5
DDEH
= 3.0–5.25 V and T
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Characteristic
Symbol
Table 26. DSPI Timing
Table 25. eMIOS Timing
t
Figure 17. eMIOS Timing
t
t
t
PCSC
t
t
PASC
t
CSC
SDC
SCK
ASC
DIS
t
A
A
(t
= T
24.4 ns
SCK
– 2 ns
Min.
23
22
—
—
4
5
L
÷ 2)
to T
80 MHz
H
.
(t
2.9 ms
SCK
+ 2 ns
Max.
25
25
—
—
—
—
÷ 2)
1
1
’
1
2
2
(t
17.5 ns
SCK
– 2 ns
Min.
15
14
—
—
4
5
112 MHz
÷ 2)
Symbol
t
t
MOPW
MIPW
(t
2.1 ms
SCK
+ 2 ns
Max.
25
25
—
—
—
—
÷ 2)
Min.
(t
15.2 ns
1
SCK
4
– 2 ns
Freescale Semiconductor
Min.
2
13
12
—
—
4
5
132 MHz
÷ 2)
(t
Max.
1.7 ms
SCK
—
—
+ 2 ns
Max.
25
25
—
—
—
—
÷ 2)
t
t
Unit
Unit
CYC
CYC
—
ns
ns
ns
ns
ns
ns
ns