MPC5553MZP132 Freescale Semiconductor, MPC5553MZP132 Datasheet - Page 46

• Manufacturer Part Number: MPC5553MZP132
• Description: IC MCU MPC5553 REV A 416-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC55xx Qorivvar

Specifications of MPC5553MZP132

• Core Processor: e200z6
• Core Size: 32-Bit
• Speed: 132MHz
• Connectivity: CAN, EBI/EMI, Ethernet, SCI, SPI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 220
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.65 V
• Data Converters: A/D 40x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-PBGA
• Processor Series: MPC5xxx
• Core: e200z6
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 7-Wire, DSPI, ESCI
• Maximum Clock Frequency: 132 MHz
• Number Of Timers: 56
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5553EVBISYS - KIT EVAL ISYSTEMS MPC5553MPC5553EVBGHS - KIT EVAL GREEN HILLS SOFTWAREMPC5553EVB - KIT EVAL MPC5553MZP132MPC5553EVBE - BOARD EVAL FOR MPC5553
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical Characteristics
3.14.2
The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one
percent. There is no minimum frequency requirement. In addition, the processor clock frequency must
exceed twice the FEC_TX_CLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER) can be programmed to transition
from either the rising- or falling-edge of TX_CLK, and the timing is the same in either case. These options
allow the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the device reference manual for details of this option
and how to enable it.
Table 29
Figure 29
46
Spec
5
6
7
8
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse-width high
FEC_TX_CLK pulse-width low
lists MII FEC transmit channel timings.
FEC_TXD[3:0] (outputs)
shows MII FEC transmit signal timings listed in
MII FEC Transmit Signal Timing
FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK
FEC_TX_CLK (input)
FEC_TX_EN
FEC_TX_ER
Figure 29. MII FEC Transmit Signal Timing Diagram
Characteristic
Table 29. MII FEC Transmit Signal Timing
MPC5553 Microcontroller Data Sheet, Rev. 3.0
5
6
7
Table
29.
Min.
35%
35%
—
5
8
65%
65%
Max
25
—
Freescale Semiconductor
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns