FDMS7602S Fairchild Semiconductor, FDMS7602S Datasheet - Page 8

• Manufacturer Part Number: FDMS7602S
• Description: MOSFET N-CH 30V DUAL POWER56
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDMS7602S

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 7.5 mOhm @ 12A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 12A, 17A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 28nC @ 10V
• Input Capacitance (ciss) @ Vds: 1750pF @ 15V
• Power - Max: 1W
• Mounting Type: Surface Mount
• Package / Case: *
• Module Configuration: Dual
• Transistor Polarity: N Channel
• Continuous Drain Current Id: 30A
• Drain Source Voltage Vds: 30V
• On Resistance Rds(on): 0.006ohm
• Rds(on) Test Voltage Vgs: 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDMS7602STR

©2010 Fairchild Semiconductor Corporation
FDMS7602S Rev.C1
Typical Characteristics (Q2 SyncFET)
100
10
Figure 21. Maximum Continuous Drain
80
60
40
20
8
6
4
2
0
1000
Figure 19. Gate Charge Characteristics
0
100
0
25
10
1
I
10
D
Current vs Case Temperature
= 17 A
-4
Limited by package
V
GS
50
= 4.5 V
10
T
C
Q
V
,
g
DD
CASE TEMPERATURE (
, GATE CHARGE (nC)
V
= 10 V
GS
V
10
75
= 10 V
DD
-3
= 20 V
20
Figure 23. Single Pulse Maximum Power Dissipation
100
V
DD
= 15 V
R
10
30
o
θ
C )
JC
-2
125
= 2
o
C/W
t, PULSE WIDTH (sec)
40
150
10
-1
Figure 22. Forward Bias Safe Operating Area
3000
1000
0.01
100
100
0.1
60
10
1
1
0.01
0.1
f = 1 MHz
V
Figure 20. Capacitance vs Drain
GS
THIS AREA IS
LIMITED BY r DS
SINGLE PULSE
T
R
T
J
A
θ
JA
= MAX RATED
= 0 V
= 25
= 120
V
V
o
DS
C
DS
0.1
to Source Voltage
, DRAIN TO SOURCE VOLTAGE (V)
o
, DRAIN to SOURCE VOLTAGE (V)
C/W
10
(
on
)
1
1
SINGLE PULSE
R
T
A
θ
JA
= 25
10
= 120
2
10
o
C
o
C/W
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10
C
rss
C
C
DC
1 s
100 us
10 ms
100 ms
1 ms
10 s
oss
iss
100
10
30
200
3