DSP56311VF150R2 Freescale Semiconductor, DSP56311VF150R2 Datasheet - Page 24

• Manufacturer Part Number: DSP56311VF150R2
• Description: IC DSP 24BIT 150MHZ 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VF150R2

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 384KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/1.7/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Specifications
2.4 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
and a V
Table 2-2. AC timing specifications, which are referenced to a device input signal, are measured in production with
respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured
with the production test machine V
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
2.4.1
2-4
Internal operation frequency with PLL
enabled
Internal operation frequency with PLL
disabled
Internal clock high period
•
•
•
Internal clock low period
•
•
•
Internal clock cycle time with PLL enabled
Internal clock cycle time with PLL disabled
Instruction cycle time
Notes:
With PLL disabled
With PLL enabled and MF ≤ 4
With PLL enabled and MF > 4
With PLL disabled
With PLL enabled and
MF ≤ 4
With PLL enabled and
MF > 4
IH
MHz and rated speed.
1.
2.
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
Characteristics
Internal Clocks
DF = Division Factor; Ef = External frequency; ET
PDF = Predivision Factor; T
See the PLL and Clock Generation section in the DSP56300 Family Manual for a details on the PLL.
OL
C
= internal clock cycle.
and V
Symbol
DSP56311 Technical Data, Rev. 8
I
CYC
T
T
T
T
Table 2-4.
f
f
H
C
C
L
OH
reference levels set at 0.4 V and 2.4 V, respectively.
C
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
0.49 × ET
0.47 × ET
0.49 × ET
0.47 × ET
= External clock cycle; MF = Multiplication Factor;
Internal Clocks
Min
—
—
—
—
—
—
—
C
C
C
C
×
×
×
×
ET
Expression
(PDF × DF)
(Ef × MF)/
2 × ET
C
DF/MF
Typ
ET
ET
× PDF ×
Ef/2
T
—
—
—
—
C
C
C
C
Freescale Semiconductor
IL
maximum of 0.3 V
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
PDF × DF/MF
0.51 × ET
0.53 × ET
0.51 × ET
0.53 × ET
Max
—
—
—
—
—
—
—
C
C
C
C
×
×
×
×