MCIMX357DVM5B Freescale Semiconductor, MCIMX357DVM5B Datasheet - Page 15

• Manufacturer Part Number: MCIMX357DVM5B
• Description: PROCESSOR MULTIMEDIA 400PBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357DVM5B

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 400-BGA
• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 400
• Operating Temperature Range: -20°C To +70°C
• Processor Type: I.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.2
Table 10
Freescale Semiconductor
Wait
Doze
Stop
Power
Mode
provides descriptions of the power modes of the i.MX35 processor.
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
RNGC internal osc is off.
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300 Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
RNGC internal osc is off
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
Power Modes
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Description
Table 10. i.MX35 Power Modes
12.4 mA
1.1
16
Typ.
QVCC (ARM/L2
mA
mA
Peripheral)
Max.
—
—
—
7.2 mA
400
7.2 mA
Typ.
MVDD/PVDD
µA
Max.
—
—
—
1.2 mA
1.2
1.2
OSC_AUDO_VDD
Typ.
OSC24M_VDD
mA
mA
Max.
—
—
—
15