MCIMX357DVM5B Freescale Semiconductor, MCIMX357DVM5B Datasheet - Page 69

• Manufacturer Part Number: MCIMX357DVM5B
• Description: PROCESSOR MULTIMEDIA 400PBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357DVM5B

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 400-BGA
• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 400
• Operating Temperature Range: -20°C To +70°C
• Processor Type: I.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.9.13.1
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4
Figure 48
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
4.9.13.1.5
Figure 49
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
Freescale Semiconductor
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DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_HSYNC
DISPB_D3_DATA
DISPB_D3_DRDY
DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
DISPB_D3_HSYNC causes the panel to start a new line.
DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_CLK
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
Synchronous Interfaces
Interface to Active Matrix TFT LCD Panels, Functional Description
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n – 1
m – 1
LINE n
m
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