MCIMX31LCVMN4C Freescale Semiconductor, MCIMX31LCVMN4C Datasheet - Page 10

IC MPU MAP I.MX31L 473-MAPBGA

MCIMX31LCVMN4C

Manufacturer Part Number
MCIMX31LCVMN4C
Description
IC MPU MAP I.MX31L 473-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX31r
Datasheets

Specifications of MCIMX31LCVMN4C

Core Processor
ARM11
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, ATA, EBI/EMI, FIR, I²C, MMC/SD, PCMCIA, SIM, SPI, SSI, UART/USART, USB, USB OTG
Peripherals
DMA, LCD, POR, PWM, WDT
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.22 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
473-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX31LCVMN4C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31LCVMN4CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
Table 6
10
Junction to Ambient (natural convection)
Junction to Ambient (natural convection)
Junction to Ambient (@200 ft/min)
1
2
3
Supply Voltage (Core)
Supply Voltage (I/O)
Input Voltage Range
Storage Temperature
ESD Damage Immunity:
Offset voltage allowed in run mode between core supplies.
HBM ESD classification level according to the AEC-Q100-002-Rev-D standard.
Integrated circuit CDM ESD classification level according to the AEC-Q100-011-Rev-B standard.
The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4.
provides the thermal resistance data for the 19 × 19 mm, 0.8 mm pitch package.
Table 5, “Absolute Maximum Ratings”
Table
Table 7, “Operating Ranges”
Table
Table 9, “Interface Frequency”
Section 4.1.1, “Supply Current Specifications”
Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions”
Stresses beyond those listed under
on page 10
ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under
page 12
extended periods may affect device reliability.
Rating
6, “Thermal Resistance Data—19 × 19 mm Package”
8,
“Specific Operating Ranges for Silicon Revision 2.0 and 2.0.1”
is not implied. Exposure to absolute-maximum-rated conditions for
Table 6. Thermal Resistance Data—19
Parameter
may cause permanent damage to the device. These are stress
Charge Device Model (CDM)
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
For these characteristics, …
Table 4. MCIMX31C Chip-Level Conditions
Human Body Model (HBM)
Table 5. Absolute Maximum Ratings
Machine Model (MM)
Four layer board (2s2p)
Single layer board (1s)
Single layer board (1s)
CAUTION
Table 5, "Absolute Maximum Ratings,"
Board
Table 7, "Operating Ranges," on
V
QVCC
NVCC
core_offset
Symbol
T
V
storage
V
Imax
×
esd
19 mm Package
max
max
3
Symbol
R
R
R
θJMA
θJA
θJA
–0.5
–0.5
–0.5
Min
–40
Topic appears …
on page 10
on page 10
on page 12
on page 12
on page 13
on page 14
on page 15
Value
46
29
38
NVCC +0.3
Freescale Semiconductor
H1C
Max
1.47
125
200
C2
3.1
15
2
1
°C/W
°C/W
°C/W
Unit
Units
mV
o
V
V
V
V
C
Notes
1, 2, 3
1, 2, 3
1, 2, 3

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