XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 21

• Manufacturer Part Number: XR16L2750IM-F
• Description: IC UART FIFO 64B DUAL 48TQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L2750IM-F

• Number Of Channels: 2, DUART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.25 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1280

xr
REV. 1.2.1
.
A
A2-A0
DDRESS
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T
ABLE
EMSR
N
MCR
FLVL
RHR
MSR
THR
FCR
SPR
R
LCR
LSR
IER
ISR
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
W
R
WR
WR
WR
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
FIFOs
Global
Mode
Pres-
B
BRG
caler
Error
Input
Sam-
pling
Rate
Bit-7
Bit-7
CD#
Bit-7
Bit-7
16X
IT
0/
0/
-7
RX FIFO
Imd/Dly#
IR Mode
RTS Int.
Enabled
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Input
Error
Inter-
Bit-6
Bit-6
TSR
Bit-6
rupt.
Bit-6
LSR
RI#
IT
0/
0/
-6
16C550 Compatible Registers
TX FIFO
Set Par-
Xoff Int.
XonAny
Source
Enable
Trigger
Empty
DSR#
B
Input
Hyst.
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
RTS
Bit-5
bit-3
INT
ity
IT
0/
0/
0/
0/
-5
21
TX FIFO
Lopback
Internal
Source
Trigger
Enable
Enable
Break
Sleep
Mode
Parity
CTS#
B
Even
Input
Hyst.
Bit-4
Bit-4
Bit-4
Bit-4
Auto
Bit-4
RTS
bit-2
INT
RX
IT
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
OP2#/INT
RX Fram-
Inversion
ing Error
Stat. Int.
Modem
Enable
Source
Enable
Enable
Enable
Output
RS485
Output
Parity
Mode
B
Delta
DMA
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Auto
Bit-3
INT
IT
-3
RX Line
(OP1#)
Enable
Source
Reset
Rsrvd
Parity
Rsrvd
B
FIFO
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
Rx/Tx
Count
RTS#
Over-
B
Word
Delta
FIFO
Error
FIFO
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
-1
Control
EFR B
Enable
Source
Enable
Length
Output
FIFOs
Ready
Count
DTR#
CTS#
Rx/Tx
B
Word
Delta
FIFO
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
IT
XR16L2750
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
FCTR[6]=0
FCTR[6]=1
C
LCR[7]=0
OMMENT