XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 26

• Manufacturer Part Number: XR16L2750IM-F
• Description: IC UART FIFO 64B DUAL 48TQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L2750IM-F

• Number Of Channels: 2, DUART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.25 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1280

XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level.
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
T
Table-A
Table-B
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
T
RIGGER
ABLE
FCTR
B
Table 10
IT
0
0
-5
T
ABLE
FCTR
B
IT
0
1
shows the complete selections. Note that the receiver and the transmitter cannot use
10: T
-4
RANSMIT AND
B
FCR
IT
0
0
1
1
0
0
1
1
-7
B
FCR
IT
0
1
0
1
0
1
0
1
-6
R
ECEIVE
B
FCR
IT
0
0
0
1
1
-5
FIFO T
BIT
FCR
26
0
0
1
0
1
-4
RIGGER
T
RIGGER
Table 10
1 (default)
R
ECEIVE
T
14
16
24
28
ABLE AND
4
8
8
L
EVEL
below shows the selections. EFR bit-4
L
1 (default)
T
EVEL
T
RANSMIT
L
RIGGER
EVEL
16
24
30
8
S
ELECTION
16C550, 16C2550,
16C2552, 16C554,
16C580
16C650A
xr
C
OMPATIBILITY
REV. 1.2.1