XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 43

• Manufacturer Part Number: XR16L2750IM-F
• Description: IC UART FIFO 64B DUAL 48TQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L2750IM-F

• Number Of Channels: 2, DUART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.25 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1280

xr
REV. 1.2.1
F
F
IGURE
IGURE
(Unloading)
(Loading data
(Unloading)
(Loading data
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
22. T
23. T
into FIFO)
into FIFO)
TX
INT*
TXRDY#
IOW#
TX
INT*
TXRDY#
IOW#
RANSMIT
RANSMIT
TX FIFO
Empty
enabled
enabled
IER[1]
IER[1]
TX FIFO
Data in
Start
Bit
S
R
R
D0:D7
EADY
EADY
ISR Read
Stop
Bit
T
Start
& I
Bit
& I
ISR is read
S
S
T
D0:D7
NTERRUPT
NTERRUPT
D0:D7
WT
TX FIFO fills up
to trigger level
TX FIFO fills up
to trigger level
Stop
Bit
T
T
T
T
S
IMING
IMING
D0:D7
D0:D7
[FIFO M
[FIFO M
T
S
S
43
TX FIFO
Full
D0:D7
D0:D7
T
T
WRI
WRI
ODE
ODE
T
T
, DMA M
, DMA M
T
T
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
SRT
SI
T
S
S
D0:D7
D0:D7
ODE
below trigger level
ODE
T
TX FIFO drops
WT
T
T
D
E
S
S
NABLED
ISABLED
ISR is read
D0:D7
D0:D7
below trigger level
TX FIFO drops
T
T
T
]
SI
]
empty location
FOR
FOR
At least 1
in FIFO
ISR Read
C
C
S
S
HANNELS
Last Data Byte
Last Data Byte
HANNELS
Transmitted
Transmitted
D0:D7
D0:D7
TXDMA#
TX FIFO
TXDMA
XR16L2750
Empty
T
SRT
T
T
A & B
A & B