DK-DEV-4CGX150N Altera, DK-DEV-4CGX150N Datasheet - Page 11

• Manufacturer Part Number: DK-DEV-4CGX150N
• Description: KIT STARTER CYCLONE IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4CGX150N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Cyclone IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2713

Chapter 2: Board Components
Board Overview
Table 2–1. Cyclone IV GX Transceiver Starter Board Components (Part 2 of 3)
© March 2010 Altera Corporation
D2
D1
D14, D15, D16,
D17, D18
D12
S7
S4
S3
S2
S1
Clock Circuitry
X1
X5
J2, J3
General User Input/Output
D5, D6, D7, D8
S5, S6
J6
Memory Devices
U12
U11
Components and Transceiver Interfaces
J7
U9
U14
Board Reference
Load LED
Error LED
Ethernet LEDs
Power LED
Configuration settings DIP
switch
CPU reset push-button switch
MAX II reset push-button
switch
PGM select push-button switch
PGM configure push-button
switch
125-MHz oscillator
50-MHz oscillator
Clock input SMAs
User LEDs
User push-button switches
Character LCD
SSRAM x18 memory
Flash x16 memory
RJ-45 connector
Gigabit Ethernet
PCI Express edge connector
Type
Illuminates when 9-V – 16-V DC power is present.
Four user LEDs. Illuminates when driven low.
Standard synchronous RAM which provides a 2-MB SSRAM port.
Provides 10/100/1000 BASE-T Ethernet connection via a Marvell
Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
Illuminates when the FPGA configuration from flash memory fails.
Shows the connection speed as well as transmit or receive activity.
Sets the configuration mode to either passive serial (flash) or active
serial (EPCS). This switch is located at the bottom of the board.
Press to reset the FPGA logic.
Press to reset the MAX II CPLD EPM2210 System Controller.
Toggles the PGM LEDs which selects the program image that loads
from flash memory to the FPGA.
Configure the FGPA from flash memory based on the PGM LEDs
setting.
125-MHz crystal oscillator for PCI Express or general use such as
memories. Multiplexed with CLKIN_SMA_P/N signals based on
CLK_SEL switch value.
50-MHz crystal oscillator for configuration purpose. This oscillator is
located at the bottom of the board.
Drive LVPECL-compatible clock inputs into the clock multiplexer
buffer (U6).
Two user push-button switches. Driven low when pressed.
Connector which interfaces to the provided 16 character × 2 line LCD
module.
Synchronous burst mode flash device which provides a 16-MB
non-volatile memory port.
88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet
MegaCore function in SGMII mode.
A Marvell 88E1111 PHY device for 10/100/1000 BASE-T Ethernet
connection. The device is an auto-negotiating Ethernet PHY with an
SGMII interface to the FPGA.
Interfaces to a PCI Express root port such as an appropriate PC
motherboard. Made of gold-plated edge fingers for up to ×1 signaling
in Gen1 mode.
Cyclone IV GX Transceiver Starter Board Reference Manual
Description
2–3