DK-DEV-4CGX150N Altera, DK-DEV-4CGX150N Datasheet - Page 19

• Manufacturer Part Number: DK-DEV-4CGX150N
• Description: KIT STARTER CYCLONE IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4CGX150N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Cyclone IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2713

Chapter 2: Board Components
Configuration, Status, and Setup Elements
© March 2010 Altera Corporation
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Flash Memory Programming
Flash memory programming is possible through a variety of methods using the
Cyclone IV GX device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the starter kit. The starter board implements the Altera PFL megafunction
for flash memory programming. The PFL megafunction is a block of logic that is
programmed into an Altera programmable logic device (FPGA or CPLD). The PFL
functions as a utility for writing to a compatible flash memory device. This pre-built
design contains the PFL megafunction that allows you to write either page 0, page 1,
or other areas of flash memory over the USB interface using the Quartus II software.
This method is used to restore the starter board to its factory default settings.
Other methods to program the flash memory can be used as well, including the
Nios
For more information on the Nios II processor, refer to the
the Altera website.
FPGA Configuration from Flash Memory
On either power-up or by pressing the PGM configure push-button switch (S1), the
MAX II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash
memory hardware page 0 or 1 based on whether PGM_LED0 or PGM_LED1 is
illuminated.
push-button switch (S1) is pressed. The PFL megafunction reads 16-bit data from the
flash memory and converts the data to PS format. This 1-bit data is then written to the
FPGA's dedicated configuration pins during configuration.
There are two pages reserved for the FPGA configuration data. The factory hardware
page is considered page 0 and is loaded upon power-up if the USER_PGM DIP switch
(S8) is set to '0'. Otherwise, the user hardware page 1 is loaded. Pressing the PGM
configure push-button switch (S1) loads the FPGA with a hardware page based on
which PGM_LED[1:0] (D3, D4) LED is illuminated.
page that loads when the PGM configure push-button switch (S1) is pressed.
Table 2–8. PGM Configure Push-Button Switch (S1) LED Settings
Note to
(1) ON indicates that the LED is illuminated while OFF indicates that the LED is not illuminated.
®
PGM_LED0
II processor.
Table
OFF
ON
ON
2–8:
Table 2–8
defines the hardware page that loads when the PGM configure
PGM_LED1
OFF
ON
ON
Cyclone IV GX Transceiver Starter Board Reference Manual
Table 2–8
Factory hardware
User hardware 1
User hardware 2
(Note 1)
Nios II Processor
Design
defines the hardware
page of
2–11