DK-DEV-4CGX150N Altera, DK-DEV-4CGX150N Datasheet - Page 20

• Manufacturer Part Number: DK-DEV-4CGX150N
• Description: KIT STARTER CYCLONE IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4CGX150N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Cyclone IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2713

2–12
Cyclone IV GX Transceiver Starter Board Reference Manual
f
1
FPGA Configuration using External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
using an external USB-Blaster device with the Quartus II Programmer running on a
PC. The external USB-Blaster is connected to the board through the JTAG connector
(J1).
By default, the FPGA is the first device in the JTAG chain. To add the MAX II CPLD
EPM2210 System Controller into the JTAG chain, set the board settings DIP switch
(S8.3) to '0'. When the starter board is plugged into a PCI Express slot, you can add the
PCI Express card into the JTAG chain by setting the board settings DIP switch (S8.4) to
'1'.
FPGA Configuration using EPCS Device
Active serial configuration can be performed using an Altera
configuration, the FPGA is the master and the EPCS128 device is the slave. The
configuration data is transferred to the FPGA on the DATA0 pin at a rate of one bit per
clock cycle. This configuration data is synchronized to the DCLK input.
Before you program the EPCS device, set the configuration DIP switch (S7) to select
the AS configuration scheme as shown in
programming the EPCS device, the design is loaded from the EPCS device to the
FPGA when you power up the board.
EPCS Programming
EPCS programming is possible through a variety of methods. One method to program
the EPCS device is to use the Serial FlashLoader (SFL), a JTAG-based in-system
programming solution for Altera serial configuration devices. The SFL is a bridge
design for the FPGA that uses the JTAG connector (J1) to access the JTAG Indirect
Configuration Device Programming File (.jic) and then uses the AS interface to
program the EPCS device. Both the JTAG and AS interfaces are bridged together
inside the SFL design.
Another method to program the EPCS device is to perform in-system programming
through the AS programming header (J12).
Other methods to program the EPCS can be used as well, including the Nios II
processor.
For more information on the following topics, refer to the respective documents:
Board Update Portal
PFL Design
PFL Megafunction
SFL Megafunction
Managing and programming
EPCS memory contents
Table 2–11 on page 2–14
Figure 2–4 on page 2–10
Topic
AN 386: Using the Parallel Flash Loader with the Quartus II Software
summarizes the board settings DIP switch controls.
AN 370: Using the Serial FlashLoader with the Quartus II Software
illustrates the JTAG chain.
Cyclone IV GX Transceiver Starter Kit User Guide
Cyclone IV GX Transceiver Starter Kit User Guide
Nios II Flash Programmer User Guide
Table 2–13 on page
Reference
Configuration, Status, and Setup Elements
© March 2010 Altera Corporation
®
2–14. After
EPCS device. During
Chapter 2: Board Components