SX1441EVK Semtech, SX1441EVK Datasheet - Page 11

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
3.2
3.2.1 CoolRISC 816 CPU
The CPU of the SX1441 is a CoolRISC816, an 8-bit low power RISC core. The instruction set is made up of 35
generic instructions coded on 22 bits and always executed in one clock cycle, including conditional jumps and 8x8
multiplications, thus providing 1 MIPS/MHz. Instructions and data memory are separated (Harvard architecture).
The 16 8-bit registers enable the use of a C compiler.
The complete CPU hardware and software description is given in the document “CoolRISC 816, 8-bit
Microprocesor Core, Hardware and Software Reference Manual”, version 4.5 which can be found on the Semtech
website (http://www.semtech.com).
3.2.2 Program Memory
The instruction memory is composed of both ROM and RAM. The ROM size is 4096 x 22-bit and stores the boot
code and the Debug-On-Chip (DoC) driver. The RAM size is 40k instructions which is completely available for the
application, except for the last 64 instructions between 0xBFB0 and 0xBFFF which are used by the Debug-on-
Chip.
The ROM is located from the address 0x0000 to the address 0x0FFF. The RAM is located in the 0x2000 to
0xBFFF range. Addresses 0x2000 to 0x2004 are jump and interrupt vectors.
3.2.3 Data Memory
The data memory space is made of 8 kbytes of RAM. The last 16 bytes between 0x3FF0 and 0x3FFF are reserved
for the Debug-On-Chip (DoC) interface. The rest of the space from 0x2000 to 0x3FEF is available for the
application. The peripheral registers are located in the page 0 of the data memory space.
© Semtech 2006
Address
0x2000
0x2001
0x2002
0x2003
0x2004
HOST PROCESSOR SYSTEM
μF μF 0xBFFF
0x2000
0h0FFF
0x0000
40k x 22 bit
4k x 22 bit
Usage
start vector
Mid priority interrupt handler
Low priority interrupt handler
High priority interrupt handler
RESERVED
ROM
RAM
Table 2 – Jump and interrupt vectors address table
Figure 4 - Memory organization
stat
i0h
i1h
i2h
i3h
iph
r0
r1
r2
r3
a
CPU
Comment
Usually set to 0x2005. The code actually begins at
0x2005
i0l
i1l
i2l
i3l
ipl
11
0x3FFF
0x3FF0
0x3FEF
0x2000
0x1FFF
0x0000
SX1441 – Bluetooth® 1.2 SoC
Peripheral
8k x 8 bit
registers
DoC
RAM
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Data Sheet