SX1441EVK Semtech, SX1441EVK Datasheet - Page 37

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
The timing of the CPU clock depends on the selection of the bit CpuSel in the RegSysClock register and is given
in Table 59.
3.9.4 Port B Digital Capabilities
The direction of each bit within PB[7:0] (input only or input/output) can be individually set using the RegPBDir
register. If RegPBDir[i] = 1, both the input and output buffers are active on the corresponding pin. If RegPBDir[i] is
0, the corresponding PB pin is an input only and the output buffer is in high impedance. After reset PB is in input
only mode; RegPBDir[i] is reset to 0.
The input values of PB are available in RegPBIn (read only). Reading is always direct - there is no debounce
function. In case of possible noise on input signals, a software debouncer with polling or an external hardware filter
has to be realized. The input buffer is also active when the port is defined as output and allows reading back of the
effective value on the pin. Data stored in RegPBOut are output at Port B if RegPBDir[x] is 1. The default value
after reset is low (0).
When a pin is in output mode (RegPBDir[i] is set), the output can be a conventional CMOS (Push-Pull) or an N-
channel Open-drain, driving the output low. By default, after reset the RegPBOpen is cleared (push-pull). If
RegPBOpen[i] is set the internal P-channel transistor in the output buffer is electrically removed and the output
can only be driven low with RegPBOut[i] cleared, or be high-impedance when RegPBOut[i] is set. The internal
pull-up or an external pull-up resistor can be used to drive the pin high. Because the P-channel transistor actually
exists (this is not a real Open-drain output) the pull-up range is limited to VDDIO_DIG + 0.2V (avoid forward bias of
the P transistor / diode).
An optional pull-up can be connected to every bit by configuring RegPBPullup. Input is pulled up when its
corresponding bit in this register is set. Default status after reset is 1, which means with pull-up. To limit power
consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an N-channel
open-drain output with the pad set (n-channel transistor disabled). In the other cases (push-pull output or open-
drain output driven low), the pull up resistors are disabled independently from RegPBPullup. After power-on reset,
the Port B is configured as an input port with pull-up activated.
The input buffer is always active. This means that the PB input should be a valid digital value at all time. An unused
pin should be configured as input pull-up or output. Violating this rule may lead to high power consumption.
3.10 COUNTERS/TIMERS
3.10.1 Features
© Semtech 2006
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4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules, each with 4 possible clock sources
Up/down counter modes
Interrupt and event generation
Capture function (internal or external source)
Rising, falling or both edge of capture signal (except for ck32k, only rising edge)
PA[3:0] can be used as clock inputs (debounced or direct, frequency divided by 2 or not)
2 x 8 bits PWM or 2 x 16 bits PWM
PWM resolution of 8, 10, 12, 14 or 16 bits
Complex mode combinations are possible
CpuSel
0
1
1/f1
Table 59 - CPU clock on PB[2] timing
Figure 17 - CPU output clock timing
1/f2
f
f
f
ckRCext
ckRCext
1
/4
37
f
f
f
ckRCext
ck32kHz
2
SX1441 – Bluetooth® 1.2 SoC
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