SX1441EVK Semtech, SX1441EVK Datasheet - Page 17

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
3.4.3 Power-On-Reset / Brownout Detector
The power-on-reset monitors both VDD_M and VDD_DIG. Upon start-up, when both voltages reach a level sufficient to ensure
correct circuit behavior, the internal reset signal is released. Then, if during operations the supply voltage drops below the
specified threshold (see
Note1 : Values above are specified across temperature range unless otherwise specified
Note2 : Values marked with asterisks are not production tested and guaranteed by design.
Table 14), the circuit goes into a reset mode.
The output of POR_VDD_M controls the pull resistor of the NRESET pad. If the NRESET pad is left unconnected
(recommended) the POR_VDD_M is propagated into the system. Otherwise, the internal nreset_system signal
may be activated by connecting the NRESET pad to the ground. The NRESET pad is active low.
The POR_VDD_M insures that VDD_M is stable so that the power management unit can operate safely. The
POR_VDD_DIG insures that VDD_DIG is correct so that the digital core can start.
3.4.4 Bus Error
The address space is assigned as shown in the memory map in Table 3. If the bit EnableBusError is set in the
register RegSysCtrl and an unused address is accessed by the processor, then a reset is generated.
3.4.5 Watchdog
Once enabled by setting the bit EnableResetWD of the RegSysCtrl register, a counter will be started and a reset
condition (watchdogreset, Figure 9) will be generated when the counter reaches its maximum value, unless the
counter is cleared by software. The counter is 3-bit wide and is clocked by the ck2Hz output of the low prescaler.
Its period is typically around 4 seconds but will depend on the clock controller configuration. The watchdog is
cleared by writing consecutively the values 0x0a and 0x03 in the RegSysWd register.
In assembler, the sequence will look like:
move RegSysWd, #0x0a
move RegSysWd, #0x03
Only writing 0x0a followed by 0x03 will clear the watchdog. If some other writing is done in and between, in
RegSysWd, then the watchdog will not be cleared.
The status of the watchdog may be checked by reading the register RegSysWd. The watchdog is a four bit counter
with a range of 0 to 7. The reset is generated when the counter reaches the value 8.
© Semtech 2006
NRESET pad
Figure 9 – POR, NRESET, and reset circuitry
POR_VDD_DIG
VDD_DIG
POR_VDD_M
VDD_M
17
SX1441 – Bluetooth® 1.2 SoC
reset
(general system reset)
resetfromportA
buserrorreset
watchdogreset
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Data Sheet