SX1441EVK Semtech, SX1441EVK Datasheet - Page 40

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When
read, these registers contain the counter value (or the captured counter value). When written, they modify the
counter comparison values. It is possible to read any counter at any time, even when the counter is running. The
value is guaranteed to be correct when the counter is running on an internal clock source. For correct acquisition of
the counter value when running on an external clock source, use one of the three following methods:
When a value is written into the counter register while the counter is in counter mode, both the comparison value is
updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount
mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the
processor clock domain and the external clock source domain, this modification of the counter value can be
postponed until the counter is enabled and receives its first valid clock edge.
In PWM mode or in capture mode, the counter value is not modified by the write operation in the counter register.
Changing to counter mode does not update the counter value (no reset in upcount, no load in downcount mode).
3.10.4 Clock Selection
The clock source for each counter can be individually selected by writing the appropriate value in the register
RegCntCtrlCk. Table 69 gives the correspondence between the binary codes used for the configuration bits
RegCntCtrlCk[1:0], RegCntCtrlCk[3:2], RegCntCtrlCk[5:4] or RegCntCtrlCk[7:6] and the clock source selected
respectively for the counters A, B, C or D.
See chapter 3.8.8 for details about the different clock sources.
Four external clocks may be provided to the counters through pins PA[3:0]. Optionally, the external clock sources
can be debounced by configuring the port PA. Additionally, the external clocks may be divided by 2 by configuring
RegCntOn[7:4].
Switching between an internal and an external clock source can only be performed while the counter is stopped.
Enabling or disabling the external clock frequency division can only happen when the counter using this clock is
stopped, or when this counter is running on an internal clock source.
3.10.5 Mode Selection
Each counter can be configured in the following modes:
Counter
Capture
PWM
Captured PWM
The counter mode is set by writing the registers RegCntConfig1 and RegCntConfig2.
© Semtech 2006
RegCntCtrlCk[i:j]
11
10
01
00
1) For slow operating counters (typically at least 8 times slower than the CPU clock), over-sample the counter
2)
3)
content and perform a majority operation on the consecutive read results to select the correct actual content
of the counter.
Stop the concerned counter, perform the read operation and restart the counter. While stopped, the
counter content is frozen and the counter does not take into account the clock edges delivered on the
external pin.
Use the capture mechanism.
Clock source for
Counter A
128 Hz timer from clock controller
ckRCext / 4
ckRCext
PA[0]
Table 69 - Counter clock selection
Counter B
PA[1]
40
Counter C
ck1kHz low prescaler output
ck32kHz low prescaler output
PA[2]
SX1441 – Bluetooth® 1.2 SoC
Counter D
PA[3]
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