SX1211I084TRT Semtech, SX1211I084TRT Datasheet - Page 31

• Manufacturer Part Number: SX1211I084TRT
• Description: IC SNGL-CHIP TXRX 32-TQFN
• Manufacturer: Semtech

Specifications of SX1211I084TRT

• Frequency: 860 ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: AMR, ISM, Security and Access
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK/OOK
• Package Type: TQFN EP
• Operating Supply Voltage (min): 2.1V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: SX1211I084TRT

In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold
detectors:
In the first example, the higher cut-off frequency enables a sequence of up to 8 consecutive “0” or “1” to be
supported, whilst the lower cut-off frequency presented in the second example allows for the correct reception of up
to 32 consecutive “0” or “1”.
The Bit Synchronizer (BitSync) is a block that provides a clean and synchronized digital output, free of glitches.
The BitSync can be disabled through the bits RXParam_Bitsync_off, and by holding pin IRQ1 low. However, for
optimum receiver performance, its use when running Continuous mode is strongly advised. With this option a
DCLK signal is present on pin IRQ_1.
The BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by
MCParam_BR. For a given bit rate, this parameter is determined by:
Rev 7 – Sept 2
ADVANCED COMMUNICATIONS & SENSING
Fixed threshold: The value is selected through the MCParam_OOK_floor_thresh register (refer to section
3.4.10.1 for further information concerning optimization of the floor threshold).
Average threshold: Data supplied by the RSSI block is averaged with the following cutoff frequency:
3.4.11. Bit Synchronizer
nd
, 2008
3.4.10.3. Alternative OOK Demodulator Threshold Modes
DCLK in continuous
Raw demodulator
To pin DATA and
RXParam
RXParam
BitSync Output
(FSK or OOK)
output
mode
BR
_
_
Figure 24: BitSync Description
OOK
OOK
IRQ_1
DCLK
DATA
64
_
_
*
cutoff
cutoff
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1
MCParam
F
XTAL
11
00
⇒
⇒
Fcutoff
Fcutoff
_
BR
32
8
BR
BR
*
*
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