MC33696FCAE Freescale Semiconductor, MC33696FCAE Datasheet - Page 24

• Manufacturer Part Number: MC33696FCAE
• Description: IC UHF RECEIVER PLL TUNED 32-QFN
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC33696FCAE

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Power - Output: 7.5dBm
• Sensitivity: -106dBm
• Voltage - Supply: 2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
• Current - Receiving: 10.3mA
• Current - Transmitting: 13mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK/OOK
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Receive Mode
Therefore, the logarithmic amplifier provides information relative to the in-band signal, whereas the LNA
AGC voltage senses the input signal over a wider band.
The RSSI information given by the logarithmic amplifier is available in:
The information from the LNA AGC is available in digital form in the four most significant bits of status
register RSSI.
The whole content of status register RSSI provides 2 ¥ 4 bits of RSSI information about the incoming
signal (see
Figure 15
The quasi peak detector (D1, R1, C1) has a charge time of about 20 μs to avoid sensitivity to spikes.
R2 controls the decay time constant of about 5 ms to allow efficient smoothing of the OOK modulated
signal at low data rates. This time constant is useful in continuous mode when S2 is permanently closed.
To allow high-speed RSSI updating in peak pulse measurement, a discharge circuit (S1) is required to reset
the measured voltage and to allow new peak detection.
S2 is used to sample the RSSI voltage to allow peak pulse measurement (S2 used as sample and hold), or
to allow continuous transparent measurement (S2 continuously closed).
The 4-bit analog-to-digital convertor (ADC) is based on a flash architecture. The conversion time is
16 × T
on a 32 × T
If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output
buffer connected to RSSIOUT is set to high impedance.
24
IF Filter Output
•
•
•
diglck
At the LNA output, the LNA AGC control voltage is used to monitor input signals in the range
–50 dBm to –20 dBm.
Analog form on pin RSSIOUT
Digital form in the four least significant bits of the status register RSSI
shows a simplified block diagram of the RSSI function.
Section 18.6, “RSSI
digclk
. As a single convertor is used for the two analog signals, the RSSI register content is updated
timebase.
Register”).
Figure 15. RSSI Simplified Block Diagram
Σ
MC33696 Data Sheet, Rev. 12
LNA AGC Out
D1
R1
C1
R2
S1
ADC
Freescale Semiconductor
MSB
S2
C2
RSSI Register
RSSIOUT
LSB