MC33696FCAE Freescale Semiconductor, MC33696FCAE Datasheet - Page 45
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MC33696FCAE
Manufacturer Part Number
MC33696FCAE
Description
IC UHF RECEIVER PLL TUNED 32-QFN
Manufacturer
Freescale Semiconductor
Type
Transceiverr
Datasheet
1.MC33696FCAE.pdf
(80 pages)
Specifications of MC33696FCAE
Frequency
304, 315, 426, 434, 868 & 915MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
FSK, OOK
Applications
General Data Transfer
Power - Output
7.5dBm
Sensitivity
-106dBm
Voltage - Supply
2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
Current - Receiving
10.3mA
Current - Transmitting
13mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Operating Frequency
915 MHz
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 20 C
Mounting Style
SMD/SMT
Operating Temperature (min)
-20C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Modulation Type
FSK/OOK
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
18.6 RSSI Register
Figure 34
Bits RSSI[7:4] contain the result of the analog-to-digital conversion of the signal measured at the LNA
output.
Bits RSSI[3:0] contain the result of the analog-to-digital conversion of the signal measured at the IF filter
output.
19
Registers are physically mapped following a byte organization. The possible address space is 32 bytes. The
base address is specified in the command byte. This is then incremented internally to address each register,
up to the number of registers specified by N[1:0], also specified by this command byte. All registers can
then be scanned, whatever the type of transmission (read or write); however, writing to read-only bits or
registers has no effect. When the last implemented address is reached, the internal address counter
automatically loops back to the first mapped address ($00).
At any time, it is possible to write or read the content of any register of Bank A and Bank B. Register access
is defined as follows:
Freescale Semiconductor
Reset Value
Bit Name
Access
R/W
R
RR
R [A]
RR [A]
Bank Access and Register Mapping
describes the RSSI Result register, RSSI.
RSSI7
Bit 7
R
0
Bit can be read and written.
Bit can be read. Write has no effect on bit value.
Bit can be read. Read or write resets the value.
Bit can be read. This returns the same value as Bank A.
Bit can be read. This returns the same value as Bank A. Read or write resets the value.
RSSI6
Bit 6
R
0
HDL1
0
0
1
1
Table 22. Header Length Selection
RSSI5
Bit 5
R
0
MC33696 Data Sheet, Rev. 12
Figure 34. RSSI Register
HDL0
0
1
0
1
RSSI4
Bit 4
R
0
RSSI3
Bit 3
R
0
HD Length
1 bits
2 bits
4 bits
6 bits
RSSI2
Bit 2
R
0
Bank Access and Register Mapping
RSSI1
Bit 1
R
0
RSSI0
Bit 0
R
0
Addr
$0C
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