AT86RF231-ZUR Atmel, AT86RF231-ZUR Datasheet - Page 51

• Manufacturer Part Number: AT86RF231-ZUR
• Description: IC RADIO TXRX 2.4GHZ 32-VQFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZUR

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.2.3
8111C–MCU Wireless–09/09
RX_AACK_ON - Receive with Automatic ACK
The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random
seed for the back-off-time random-number generator in the AT86RF231.
The MAX_BE and MIN_BE register bits (register 0x2F) sets the maximum and minimum CSMA
back-off exponent (according to [1]).
The general functionality of the RX_AACK procedure is shown in
The gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 com-
pliant frames, refer
procedures are exceptions for specific operating modes or frame formats, refer to
7.2.3.3 “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page
The frame filtering operations is described in detail in
61.
In RX_AACK_ON state, the radio transceiver listens for incoming frames. After detecting a valid
PHR, the radio transceiver parses the frame content of the MAC header (MHR), refer to
8.1.2 “MAC Protocol Layer Data Unit (MPDU)” on page
Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indicated
if the frame filter does not match and the FCS is invalid. Otherwise, the interrupt IRQ_3
(TRX_END) is issued after the completion of the frame reception. The microcontroller can then
read the frame. An exception applies if promiscuous mode is enabled; see
figuration of IEEE Scenarios” on page
even if the FCS fails.
If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 section
7.2.1) matches one of the configured addresses, dependent on the addressing mode, an
address match interrupt IRQ_5 (AMI) is issued, refer to
page
PAN-ID and IEEE address). Frame filtering as described in
page 61
During reception the AT86RF231 parses bit [5] (ACK Request) of the frame control field of the
received data or MAC command frame to check if an ACK reply is expected. In that case and if
the frame passes the third level of filtering, see IEEE 802.15.4-2006, section 7.5.6.2, the radio
transceiver automatically generates and transmits an ACK frame.
The content of the frame pending subfield of the ACK response is set by register bit
AACK_SET_PD (register 0x2E, CSMA_SEED_1) when the ACK frame is sent in response to a
data request MAC command frame, otherwise this subfield is set to 0. The sequence number is
copied from the received frame.
Optionally, the start of the transmission of the acknowledgement frame can be influenced by
register bit AACK_ACK_TIME. Default value (according to standard IEEE 802.15.4) is 12 sym-
bol times after the reception of the last symbol of a data or MAC command frame.
If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no acknowledgement
frame is sent even if an acknowledgment frame was requested. This is useful for operating the
MAC hardware accelerator in promiscuous mode, see
Scenarios” on page
61. The expected address values are to be stored in registers 0x20 - 0x2B (Short address,
is also valid for Basic Operating Mode.
55.
Section 7.2.3.2 “Configuration of IEEE Scenarios” on page
55, in that case an IRQ_3 (TRX_END) interrupt is issued,
Section 7.2.3.5 “Frame Filtering” on page
80.
Section 7.2.3.2 “Configuration of IEEE
Section 7.2.3.5 “Frame Filtering” on
Section 7.2.3.5 “Frame Filtering” on
Figure 7-9 on page
AT86RF231
Section 7.2.3.2 “Con-
58.
55. All other
53.
Section
Section
51