XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 13

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XRD9836ACG

Manufacturer Part Number
XRD9836ACG
Description
IC 16B CCD/CIS SIG PROC 48TSSOP
Manufacturer
Exar Corporation
Datasheet

Specifications of XRD9836ACG

Package / Case
48-TSSOP (0.240", 6.10mm Width)
Number Of Bits
16
Number Of Channels
3
Power (watts)
500mW
Voltage - Supply, Analog
3 V ~ 3.6 V
Voltage - Supply, Digital
3 V ~ 3.6 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

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xr
xr
In addition to the above requirement for LCLMP on a
line by line basis there is an additional requirement
for a one time LCLMP upon power-up to provide the
AC coupling capacitor’s initial charge. The one time
LCLMP pulse width can also be determined from the
Cmax equation above. A typical value, using 1 nf cap,
with initial charge of 3V (Vr - Vc), and a BSAMP pulse
width of 25ns, is estimated to be 1.4us. This is equiv-
alent to one time LCLMP of 56 OB pixels upon power
up.
3-CHANNEL CDS MODE:
This mode allows simultaneous CDS of the red,
green and blue inputs. Black-level sampling occurs on
each pixel and is equal to the width of the BSAMP
sampling input. The black level is held on the sam-
pling edge of BSAMP and the PGA will immediately
begin to track the signal input until the sampling edge
of VSAMP.
At the end of the video sampling phase, the differ-
ence between the reference and video levels is invert-
ed, amplified, and offset depending on the contents of
the PGA gain and offset registers. The RGB channels
are then sequentially converted by a high-speed A/D
converter. Converted data appears on the data output
bus after 9 ADCLK cycles. The red channel is syn-
chronized on the rising edge of the first ADCLK after
the sampling edge of VSAMP. The power-up default
mode is for CDS sampling a CCD input.
1-CHANNEL CDS MODE:
The 1-Channel CDS mode allows high-speed acqui-
sition and processing of a single channel. The timing,
clamp and buffer configurations are similar to the 3-
channel mode described previously. To select a single
channel input, the color bits of configuration selected
by CHAN[1:0] bits, in the MODE register, must be set
to the appropriate value. The A/D input will begin to
track the selected color input on the next positive
edge of ADCLK. If the configuration is toggled from a
single color mode to 3-channel mode, RGB scanning
will not occur until the circuit is re-synchronized on
the sampling edge of VSAMP.
CIS MODE:
The AFE can be configured for inputs from a CCD or
a CIS type device by setting the CCD_CIS bit. For
CIS mode, the following interface features are provid-
ed:
1. DC Coupled Inputs.
2. Gain Range is 0.5 to 5 with 10 bit resolution.
3. It is assumed that CIS Sample and Hold Outputs
and DC offset buffer have low output impedanc-
es(~50 ohms).
13
4. VSAMP should have typ > 25ns pulse width.
5. LCLMP is not needed for CIS Applications. (except
for APOAM even and odd selection)
6. Input Voltage Range:
F
3-CHANNEL CIS AND S/H MODE
The XRD9836 also supports operation for Contact
Image Sensor (CIS) and S/H applications. The red
channel is synchronized on the rising edge of the first
ADCLK after the sampling edge of VSAMP.
In this mode of operation, the BSAMP input is con-
nected to DGND, and input sampling occurs on the
falling edge of VSAMP(VSAMP_POL=0).
1-CHANNEL CIS AND S/H MODE:
The 1-channel CIS S/H mode allows high-speed ac-
quisition and processing of a single channel. The tim-
ing, clamp and buffer configurations are similar to the
3-channel mode. In single channel mode one color
channel is selected using CHAN[1:0]. If the configura-
tion is toggled from single color to 3-channel mode,
RGB scanning will not occur until the circuit is re-syn-
chronized by the first sampling edge of VSAMP.
F
IGURE
IGURE
W avef or m
Vcm (DCoffset)
NC
CIS Signal @ Vin+ = 0 to 1.2 V above Vcm offset
C IS
Vcm @ Vin- = 0 to 1.4 V
CIS Signal
8. CIS S
Vcm
9. CIS W
CDS
Pixel N-1
Dynamic
Offset
10 bit
DAC
+
IGNAL
AVEFORM
Pixel N
10 bit
P
PGA
ATH
16-BIT PIXEL GAIN AFE
INVSR
-D
Pixel N+1
EFINITION OF TERMS
Offset
10 bit
Fine
DAC
+
Pixel N+2
MUX
3:1
XRD9836
REV. 1.0.0
Pixel N+3
ADC

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