XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 14

• Manufacturer Part Number: XRD9836ACG
• Description: IC 16B CCD/CIS SIG PROC 48TSSOP
• Manufacturer: Exar Corporation

Specifications of XRD9836ACG

• Package / Case: 48-TSSOP (0.240", 6.10mm Width)
• Number Of Bits: 16
• Number Of Channels: 3
• Power (watts): 500mW
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
TIMING - CLOCK BASICS:
The XRD9836 has 4 clock signals BSAMP, VSAMP,
ADCLK and LCLMP. These inputs control the sam-
pling, clamping and synchronization functions of the
device.
The pixel rate clocks are BSAMP, VSAMP and AD-
CLK. BSAMP controls the sampling of the black refer-
ence level of a CCD input signal. VSAMP controls the
sampling of the video level of a CCD or CIS output
signal. The ADCLK controls the internal sampling of
the PGA by the ADC and ADC operation.
The line rate clock, LCLMP, performs the clamping
and synchronization functions. The clamp function
sets the bias point for the external AC coupling ca-
pacitor on the inputs. Synchronization defines the odd
pixel in the APOAM mode.
CLOCK POLARITY
Each of the 4 timing signals has a separate polarity
control bit in the CONTROL register. Figure 10 shows
the logic implementation of the polarity control. If the
polarity bit is low (default) BSAMP and VSAMP sam-
ple on the falling edge, LCLMP is active high and AD-
CLK must be low during the VSAMP falling edge. See
timing examples if Figure 17 and Figure 18
If any of the external timing signals are inverted from
the default timing simply write a “1” to the appropriate
polarity bit to compensate.
DELAY CONTROL
One of the more difficult tasks in designing a scanner
is optimizing the pixel and interface (data output &
OGI) timing for a CCD, CDS and ADC. The
F
IGURE
BSAMP
VSAMP
ADCLK
LCLMP
10. C
LOCK
Polarity
Polarity
Polarity
Polarity
P
OLARITY AND
Delays
D
ELAYS
Clock
Logic
ADC
AFE
OGI
14
XRD9836 has included a programmable delay func-
tion to help simplify this job.
There are four serial interface registers, DelayA, De-
layB, DelayC and DelayD, used to program various
delays of the pixel timing and Data and OGI bus tim-
ing. Each register is divided into 2 delay parameters.
Each delay parameter is 4 bits wide.
DelayA[7:4] controls the OGI sampling delay. These
bits program the delay of the ADCLK used to sample
the OGI input bus. Delay is added in 1ns increments.
See Figure 12.
DelayA[3:0] controls the ADCDO delay. These bits
are used to program the timing delay added to the
ADCDO data bus updates. Delay is added in 1ns in-
crements. See Figure 11.
DelayB[7:4] controls the amount of delay added to the
leading edge of BSAMP. Delay to the leading edge
will be added in 0.5ns increments. This can help to
position the leading edge of the internal BSAMP away
from the reset pulse of the CCD input. See Figure 11.
DelayB[3:0] controls the amount of delay added to the
trailing edge of BSAMP. Delay to the trailing edge will
be added in 0.5ns increments. This will allow for ad-
justment of the Black Level sampling position by the
internal BSAMP. See Figure 11.
DelayC[7:4] controls the amount of delay added to
the leading edge of VSAMP. Delay will be added in
0.5ns increments. This can help to position the lead-
ing edge of the internal VSAMP to track the video
portion of the CCD input. See Figure 11.
DelayC[3:0] controls the amount of delay added to
the trailing edge of VSAMP. Delay will be added in
0.5ns increments. This will allow for adjustment of the
Video Level sampling position by the internal VSAMP.
See Figure 11.
DelayD[7:4] controls the amount of delay added to
the VSAMP OGI. The internal VSAMP_OGI is used
to transfer the input OGI register data to the PGA and
OFFSET control. Delay is added in 1ns increments.
Please note the falling edge of the internal
VSAMP_OGI must occur before the rising edge of
the OGI sampling clock. See Figure 12.
DelayD[3:0] controls the amount of delay added to
the ADCLK. Delay is added to the internal ADCLK in
0.5ns increments. See Figure 11.
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