XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 24

• Manufacturer Part Number: XRD9836ACG
• Description: IC 16B CCD/CIS SIG PROC 48TSSOP
• Manufacturer: Exar Corporation

Specifications of XRD9836ACG

• Package / Case: 48-TSSOP (0.240", 6.10mm Width)
• Number Of Bits: 16
• Number Of Channels: 3
• Power (watts): 500mW
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Delay
Registers
DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used to sample the
Offset-Gain-Inputs (OGI). Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 1000 = 7 ns. OGI_DLY should
be larger than VSAMP_OGI_DLY.
DelayA[3:0] - Controls the ADCO_DLY. These bits are used to program the timing delay of ADCO outputs in relation to
ADCLK. Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 0000 = 0ns. This is used to adjust setup and hold
times of the output, for the ASIC chip.
DelayB[7:4] - Controls the BSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayB[3:0] - Controls the BSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[7:4] - Controls the VSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayC[3:0] - Controls the VSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal
VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
DelayD[7:4] - Controls the VSAMP_OGI_DLY. These bits set the delay for the internal VSAMP that is used to transfer
the OGI register data to the PGA & OFFSET control registers.
DelayD[3:0] - Controls the ADC_DLY. These bits set the delay of the internal clock used for ADC operation. Code 0000
is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
(10010)
DelayC
(10000)
default
default
default
default
DelayA
(10001)
DelayD
(10011)
DelayB
D9
D8
DelayA
DelayB
DelayC
DelayD
D7
[7]
[7]
[7]
[7]
1
0
0
0
DelayA
DelayB
DelayC
DelayD
D6
[6]
[6]
[6]
[6]
24
0
0
0
0
DelayA
DelayB
DelayC
DelayD
D5
[5]
[5]
[5]
[5]
0
0
0
0
DelayA
DelayD
DelayB
DelayC
D4
[4]
[4]
[4]
[4]
0
0
0
0
DelayA
DelayB
DelayC
DelayD
D3
[3]
[3]
[3]
[3]
0
0
0
0
DelayA
DelayB
DelayC
DelayD
D2
[2]
[2]
[2]
[2]
0
0
0
0
xr
xr
DelayA
DelayB
DelayC
DelayD
D1
[1]
[1]
[1]
[1]
0
0
0
0
DelayA
DelayD
DelayB
DelayC
D0
[0]
[0]
[0]
[0]
0
0
0
0