XR16C854IJ-F Exar Corporation, XR16C854IJ-F Datasheet - Page 19
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XR16C854IJ-F
Manufacturer Part Number
XR16C854IJ-F
Description
IC UART FIFO 128B QUAD 68PLCC
Manufacturer
Exar Corporation
Datasheet
1.XR16C854IV-F.pdf
(54 pages)
Specifications of XR16C854IJ-F
Features
*
Number Of Channels
4, QUART
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
No. Of Channels
4
Data Rate
2Mbps
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
No. Of Pins
68
Termination Type
SMD
Uart Features
Tx/Rx FIFO Counters
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C854IJ-F
Manufacturer:
EXAR
Quantity:
4
Company:
Part Number:
XR16C854IJ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
xr
REV. 3.0.1
When software flow control is enabled
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) match the
programmed values, the 854 will halt transmission as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 854 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 854 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters
selected, the 854 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the 854 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 854 sends the Xoff-
1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the
854 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level
below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto
RTS Hysteresis value in
selected.
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The 854 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
The 854 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See
characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.16
2.17
2.18
RX T
Auto Xon/Xoff (Software) Flow Control
Infrared Mode
RIGGER
Special Character Detect
16
24
28
8
L
(See Table
EVEL
INT P
Table
17) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
T
ABLE
IN
A
16
24
28
8
CTIVATION
15.
7: A
Table 7
UTO
(See Table
X
Figure 12
ON
below explains this when Trigger Table-B (See
X
/X
(
OFF
CHARACTERS IN RX FIFO
OFF
17), the 854 compares one or two sequential receive data
C
19
(S
HARACTER
below.
OFTWARE
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
16*
24*
28*
8*
(
S
) S
) F
ENT
LOW
)
C
ONTROL
X
(
CHARACTERS IN RX FIFO
ON
C
HARACTER
16
24
0
8
XR16C854/854D
(
S
) S
Table
ENT
)
11) is