XR16C854IJ-F Exar Corporation, XR16C854IJ-F Datasheet - Page 37

• Manufacturer Part Number: XR16C854IJ-F
• Description: IC UART FIFO 128B QUAD 68PLCC
• Manufacturer: Exar Corporation

Specifications of XR16C854IJ-F

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• No. Of Channels: 4
• Data Rate: 2Mbps
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Termination Type: SMD
• Uart Features: Tx/Rx FIFO Counters
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
REV. 3.0.1
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
This register controls the XR16C854 new functions that are not available in ST16C554 or ST16C654.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
FCTR[2]: IrDA RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
The Auto RS-485 Direction Control is not available in the XR16C854. See XR16C864. However, this bit
changes the TX Ready Interrupt behavior. See
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
FCTR[6]: Scratchpad Swap
•
•
FCTR[7]: Programmable Trigger Register Select
•
•
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
4.17
4.18
4.19
Logic 0 = Select RX input as encoded IrDA data (Idle state will be logic 0).
Logic 1 = Select RX input as inverted encoded IrDA data (Idle state will be logic 1).
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive holding register can be read via scratch pad register when this bit is set.
Enhanced Mode Select Register is selected when it is written into.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
Table
Table 11
FIFO Data Count Register (FC) - Read-Only
Enhanced Feature Register (EFR) - Read/Write
Feature Control Register (FCTR) - Read/Write
14.
for more details.
FCTR
B
IT
0
0
1
1
-5
T
ABLE
FCTR
B
IT
0
1
0
1
-4
16: T
Table
Table
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
RIGGER
17). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
37
3.
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
T
ABLE
T
ABLE
Table 15
S
ELECT
for more details.
XR16C854/854D