XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 113

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XRT94L31IB

Manufacturer Part Number
XRT94L31IB
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT94L31IB

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

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REV. 1.0.1
N
Table 15
Egress Direction) for DS3/E3 Applications and when the DS3/E3 Framer block has been configured to output
the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/STS_1_NEG_OUT signal upon
the rising edge of DS3/E3/STS_1_CLOCK_OUT.
Table 16
Egress Direction) for DS3/E3 Applications and when the DS3/E3 Framer block has been configured to output
the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/STS_1_NEG_OUT signals upon
the falling edge of DS3/E3/STS_1_CLOCK_OUT.
Table 17
Egress Direction) for STS-1/STM-0 Applications and when the Transmit STS-1 TOH Processor block has been
configured to output the DS3/E3/STS_1_DATA_OUT signal upon the rising edge of DS3/E3/
STS_1_CLOCK_OUT.
F
DS3/E3/STS-1 LIU I
1.3.7
1.3.8
S
S
OTE
IGURE
YMBOL
YMBOL
t11
t11
: The value for t11 is presented in
17. A
T
T
presents information on the Timing Parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
presents information on the Timing Parameters for the DS3/E3/STS-1 LIU Interface Signal (in the
DS3/E3/STS_1_CLOCK_OUT
ABLE
ABLE
Egress Timing for DS3/E3 Applications
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
& DS3/E3/STS_1_NEG_OUT output delay
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
& DS3/E3/STS_1_NEG_OUT output delay
Egress Timing for STS-1/STM-0 Applications
DS3/E3/STS_1_DATA_OUT
DS3/E3/STS_1_NEG_OUT
N
I
15: T
16: T
LLUSTRATION OF THE
NTERFACE
IMING
IMING
A
A
PPLICATIONS
PPLICATIONS
I
I
NFORMATION FOR THE
NFORMATION FOR THE
(
IN THE
Tables 15
(
W
(
FALLING EDGE OF
R
RISING EDGE OF
D
D
AVEFORMS OF THE
ECEIVE
ESCRIPTION
ESCRIPTION
/E
,
16
GRESS
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
E
E
t11
GRESS
GRESS
,
113
17
DS3/E3/STS_1_CLOCK_OUT)
DS3/E3/STS_1_CLOCK_OUT)
D
.and
IRECTION
DS3/E3/STS-1
DS3/E3/STS-1 LIU I
DS3/E3/STS-1 LIU I
18
)
SIGNALS THAT ARE OUTPUT FROM THE
NTERFACE FOR
NTERFACE FOR
2.1ns
1.6ns
M
M
IN
IN
.
.
T
T
DS3/E3
DS3/E3
YP
YP
XRT94L31
.
.
7.8ns
6.5ns
M
M
AX
AX
.
.

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