XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 62

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
AG16
PIN #
TXHDLCDAT_2_3
STS1TXA_2_D3
SIGNAL NAME
SSI_NEG
I/O
I/O
TTL/
CMOS
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 2 - Data Bus Input
pin number 3/Transmit High-Speed HDLC Controller Input Interface
block - Channel 2 - Input Data Bus - Pin 3/Slow-Speed Interface -
Negative Polarity Data Input/Output signal:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 2 is enabled.
If STS-1 Telecom Bus (Channel 2) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 3 -
STS1TXA_2_D3:
This input pin along with STS1TXA_2_D[7:4] and STS1TXA_2_D[2:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 2. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_2.
If the STS-1 Telecom Bus Interface (associated with Channel 1) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 2 - Data Bus Input
Pin # 3 TXHDLCDAT_2_3:
In this mode, this input pin will function as Bit 3 within the Transmit High-
Speed HDLC Controller Input Interface block - Input Data Bus (e.g., the
TxHDLCDat_2[7:0] input pins).The Transmit High-Speed HDLC Control-
ler Input Interface block will provide the System-Side Terminal equip-
ment with a byte-wide Transmit High-Speed HDLC Controlller clock
output signal (TxHDLCClk_2).
The Transmit High-Speed HDLC Controller Input Interface block will
sample the data residing on this input pin (along with the rest of the
TxHDLCDat_2[7:0] input pins) upon the rising edge of the TxHDLCClk_2
clock output signal.
If the XRT94L31 is configured to operate in the DS3/E3/STS-1 to
STS-3/STM-1 Mapper Mode - Slow-Speed Interface for Ingress Path
- Negative-Polarity Data Input/Output - SSI_NEG:
This pin along with the SSI_POS and SSI_CLK pins function as the
Slow-Speed Interface for the Ingress Direction Signal Path Input/Output
Port. which can be configured to function as either an Input (ADD) or
Output (DROP) port.
If the SSI Port is configured to operate as an Input (ADD) Port:
In this configuration this port can be configured to accept a DS3, E3 or
STS-1 signal (from external circuitry) and it will ADD this DS3/E3/STS-1
signal into the Selected Ingress Direction Channel within the XRT94L31.
In this mode, the SSI_NEG will function as the Negative-Polarity Portion
of the DS3/E3/STS-1 signal that is being ADDed. In this mode, the SSI
Port will sample the data (being applied to this pin) upon the rising edge
of SSI_CLK.
If the SSI Port is configured to operate as an Output (DROP) Port:
If the Slow-Speed Interface is configured to operate as an Output Port,
then this port can be configured to output (or DROP out) the Selected
Ingress Direction Channel within the XRT94L31.
In this mode, the SSI_NEG will output the Negative Polarity portion of
this selected Ingress Direction signal. This output pin will be updated
upon the falling edge of the SSI_CLK output pin.
62
DESCRIPTION
REV. 1.0.1