XRT94L31IB Exar Corporation, XRT94L31IB Datasheet - Page 89

• Manufacturer Part Number: XRT94L31IB
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
W6
W5
F7
F5
F4
D3
E4
E5
U6
U5
SIGNAL NAME
RXCAPP_R
RXCAPN_R
REFCLK45
RXCAPP
RXCAPN
TRST
TDO
TMS
TCK
TDI
I/O
O
I
I
I
I
I
I
I
I
I
TTL
CMOS
TTL
TTL
TTL
TTL
ANA-
LOG
ANA-
LOG
ANAL0
OG
ANA-
LOG
TYPE
FILTERING CAPACITORS
MISCELLANEOUS PINS
DS3 Reference Clock Input for the Jitter Attenuator within the DS3/
E3 Mapper Block:
To operate any of the channels of the XRT94L31 in the DS3 Mode, apply
a clock signal with a frequency of 44.736±20ppm to this input pin.
This input pin functions as the timing reference for the DS3/E3/STS-1 Jit-
ter Attenuator (within the DS3/E3 Mapper block) for DS3 applications.
For DS3 Applications, the DS3/E3 Framer block will use this input clock
signal, as a timing source in order to transmit the DS3 AIS Pattern, in the
Egress Direction (e.g., from the XRT94L31 to the DS3/E3/STS-1 LIU
IC).
If the user does not intend to operate any of the three (3) channels in the
DS3 Mode, or if the user intends to configure the XRT94L31 to operate
in the SFM Mode, connect this input pin to GND.
Test Data Out: Boundary Scan Test data output
TEST Data In: Boundary Scan Test data input:
N
JTAG Test Reset Input
Test clock: Boundary Scan clock inputNote:
N
Test Mode Select: Boundary Scan Mode Select inputNote:
N
External Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor, which is
used to minimize jitter peaking.
External Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor, which is
used to minimize jitter peaking.
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor, which is
used to minimize jitter peaking.
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor, which is
used to minimize jitter peaking.
OTE
OTE
OTE
BOUNDARY SCAN
: This input pin should be pulled "Low" for normal operation.
: This input pin should be pulled "Low" for normal operation.
: This input pin should be pulled "Low" for normal operation.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
89
DESCRIPTION
XRT94L31