XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 110
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
N
These timing requirements apply to both the Primary and the Redundant Receive STS-3/STM-1 PECL
Interface blocks.
The user should be aware of the following things about the Ingress DS3/E3/STS-1 Interface Timing.
F
STM-1 PECL I
1.
2.
3.
1.3.3
1.3.3.1
OTE
IGURE
S
YMBOL
:
t6
t7
If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
configured to sample the DS3/E3/STS_1_DATA_IN and the DS3/E3/STS_1_NEG_IN input pins upon
either the rising or falling edge of DS3/E3/STS_1_CLOCK.
If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1 TOH
Processor block will be operating in the Single-Rail Mode (e.g., the Receive STS-1 TOH Processor block
will ONLY sample the DS3/E3/STS_1_DATA_IN input signal.
STS_1_NEG_IN input signal.
Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1
TOH Processor block can be configured to sample the DS3/E3/STS_1_DATA_IN input signal, upon
either the rising or falling edge of DS3/E3/STS_1_CLOCK_IN.
Table 10
15. A
DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION
RxL_CLKL_p
RxL_CLKL_n
RxL_Data_p
RxL_Data_n
RxL_DATA to rising edge of RxL_CLKL set-up time requirements
Rising edge of RxL_CLKL to RxL_DATA hold time requirements
N
Ingress DS3/E3/STS-1 Interface Timing
T
NTERFACE
I
ABLE
presents information on the Timing parameters for the Receive STS-3/STM-1 PECL Interface
LLUSTRATION OF THE
10: T
IMING
I
NFORMATION FOR THE
D
W
ESCRIPTION
AVEFORMS OF THE
t6
110
R
ECEIVE
S
IGNALS THAT ARE
STS-3/STM-1 PECL I
t7
It will not sample the DS3/E3/
200ps
200ps
I
M
NPUT VIA THE
IN
.
NTERFACE
T
R
YP
ECEIVE
.
STS-3/
REV. 1.0.1
M
AX
.
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