XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 49

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
B12
TXHDLCDAT_0_6
STS1TXA_0_D6
TXSBDATA_6_0
SIGNAL NAME
TXDS3DATA_0
I/O
I
TTL
TYPE
Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input
pin number 6/Transmit High-Speed HDLC Controller Input Interface
block - Channel 0 - Input Data Bus - Pin 6/Transmit DS3/E3 Serial
Data Input - Channel 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 0 is enabled.
If STS-1 Telecom Bus (Channel 0) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 6:
STS1TXA_0_D6:
This input pin along with STS1TXA_0_D7 and STS1TXA_0_D[5:0] func-
tion as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus
for Channel 0. The Transmit STS-1 Telecom Bus interface will sample
and latch this pin upon the falling edge of STS1TXA_CLK_0.
If the STS-1 Telecom Bus Interface (associated with Channel 0) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode -Transmit High-Speed HDLC
Controller Input Interface block - Data Bus Input pin # 6 - Channel 0 -
TxHDLCDAT_0_6:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 6
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_0[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_0[7:0] input pins) upon the rising edge of the TxHDLCClk_0
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/
E3 Framer over STS-3/STM-1 Mapper Mode - Transmit Payload Data
Input Interface -Channel 0 - Transmit DS3/E3 Serial Data Input -
TxDS3DATA_0:
If the XRT94L31 is configured to operate in the Clear-Channel Framer
over STS-3/STM-1 Mapper mode, then this input pin functions as the
Transmit Payload Data Serial Input pin for Channel 0. In this case, the
System-Side terminal equipment is expected to apply all outbound data
(which is intended to be carried via the DS3 or E3 payload bits) to this
input pin.
The Transmit Payload Data Input Interface will sample the data, residing
at the TxDS3DATA_0 input pin, upon the rising edge of TxInClk.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
49
DESCRIPTION
XRT94L31