XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 90

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
AA1
G2
H5
K4
N1
N2
K1
J3
J2
SIGNAL NAME
FL_TSTCLK
REFSEL_L
Test Mode
VDCTST1
VDCTST2
ANALOG
SFM
N/C
N/C
I/O
O
O
O
O
I
I
I
TTL
TTL
TTL
CMOS
ANA-
LOG
ANA-
LOG
ANA-
LOG
TYPE
Clock Synthesizer Block Select:
This input pin is used to configure the Transmit SONET circuitry (within
the XRT94L31) to use either of the following clock signals as its timing
source.a.
Setting this input pin "High" configures the Transmit SONET circuitry
within the XRT94L31 to use the Clock Synthesizer block as its timing
source. In this mode, the user can supply either a 19.44MHz,
38.88MHz, 51.84MHz or 77.76MHz clock signal to the REFTTL input
pin.
Setting this input pin "Low" by-passes the Clock Synthesizer block. In
this case, the user MUST supply a 19.44MHz clock signal to the
REFTTL input pin in order to insure proper performance.
Single Frequency Mode (SFM) Select:
This input pin is used to configure the three Jitter Attenuator (SONET/
SDH De-Sync) blocks of the XRT94L31 to operate in the Single-Fre-
quency Mode (SFM). If the XRT94L31 has been configured to operate
in the SFM Mode, then the user only needs to supply a 12.288MHz clock
signal to the REFCLK51 input pin. In this case, the user does not need
to supply a 44.736MHz clock signal to the REFCLK45 input pin, nor a
34.368MHz clock signal to the REFCLK34 input pin. The SFM PLL
(within the XRT94L31) will internally synthesize the appropriate
44.736MHz, 34.368MHz or 51.84MHz clock signals, and will route these
signals to the appropriate channels (within the chip) depending upon the
data rate that they are configured to operate in.
Setting this input pin to a logic "Low" disables the Single-Frequency
Mode. In this mode, the user must supply all of the appropriate frequen-
cies to the REFCLK34, REFCLK45 and REFCLK51 input pins.
Setting this input pin to a logic "High" configures the XRT94L31 to oper-
ate in the Single-Frequency Mode.
Test Mode Input Pin:
Connect this input pin "Low" for normal operation.
JA Testing Clock:
This pin is used for JA testing purposes.
Analog Output Pin:
This output analog pin is used for testing purposes.
DC Test Pin:
This pin is used for internal DC test, for example, it can be used to test
for DC current, DC voltage.
DC Test Pin:
This pin is used for internal DC test, for example, it can be used to test
for DC current, DC voltage.
NO-CONNECT PINS
a. The Directly-Applied 19.44MHz clock signal, which is applied to
b. The output of the Clock Synthesizer block (within the chip).
the REFTTL input pin (P1) or,b.
90
DESCRIPTION
REV. 1.0.1